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Honored ContributorVerilog Program - Need help with it
Hello all,
I have no clue about Verilog and I want to understand a bit of program that might be useful to me. Would you happen to know what this means? I am trying to convert that into VHDL. I guess module is entity, wire is signal and the ports are inputs and outputs but what does the rest of the program mean? `define rom_size 6'd8 module CLOCK_500 ( CLOCK, CLOCK_500, DATA, END, RESET, GO, CLOCK_2 ); input CLOCK; input END; input RESET; output CLOCK_500; output [23:0]DATA; output GO; output CLOCK_2; reg [10:0]COUNTER_500; wire CLOCK_500=COUNTER_500[9]; wire CLOCK_2=COUNTER_500[1]; reg [15:0]ROM[`rom_size:0]; reg [15:0]DATA_A; reg [5:0]address; wire [23:0]DATA={8'h34,DATA_A}; wire GO =((address <= `rom_size) && (END==1))? COUNTER_500[10]:1; always @(negedge RESET or posedge END) begin if (!RESET) address=0; else if (address <= `rom_size) address=address+1; end reg [7:0]vol; always @(posedge RESET) begin vol=vol-1;end always @(posedge END) begin // ROM[0]= 16'h1e00; ROM[0]= 16'h0c00; //power down ROM[1]= 16'h0ec2; //master ROM[2]= 16'h0838; //sound select ROM[3]= 16'h1000; //mclk ROM[4]= 16'h0017; // ROM[5]= 16'h0217; // ROM[6]= {8'h04,1'b0,vol[6:0]}; // ROM[7]= {8'h06,1'b0,vol[6:0]}; //sound vol //ROM[4]= 16'h1e00; //reset ROM[`rom_size]= 16'h1201;//active DATA_A=ROM[address]; end always @(posedge CLOCK ) begin COUNTER_500=COUNTER_500+1; end endmodule7 Replies
Altera_ForumThe correspondences between verilog and VHDL terminology are correct.
A "module" in verilog however corresponds to both a "entity" and "architecture" combination in VHDL. In Quartus-II you can use an instance of this module in verilog in a higher level VHDL description. It is easy to mix VHDL and verilog.- Altera_Forum
CLOCK_2 is a half frequency CLOCK.
GO is the 1/2048 frequency CLOCK when END is high and address is in desired region. Else , GO is high. When END assert, the ROM read out its next data to DATA[15:0] port. The DATA[23:16] stuck at 8'h34. And the ROM initial value is: ROM[0]= 16'h0c00; //power down ROM[1]= 16'h0ec2; //master ROM[2]= 16'h0838; //sound select ROM[3]= 16'h1000; //mclk ROM[4]= 16'h0017; // ROM[5]= 16'h0217; // ROM[6]= {8'h04,1'b0,vol[6:0]}; // ROM[7]= {8'h06,1'b0,vol[6:0]}; //sound vol - Altera_Forum
Ok,
So if I want to write this in VHDL? How would I do it? Should I assign values the same values for ROM in VHDL terms? - Altera_Forum
Well I had a longer answer here but the forum didn't save it.....
With an HDL file open in Quartus try "Edit" --> "Insert Template" and you'll find to code fragments you can use. Here is a good document as well: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf - Altera_Forum
So, would that part translate to:
signal ROM : rom_type; After the begin of architecture ROM(0)<=X"0c00"; ROM(1)<=X"0ec2"; ROM(2)<=X"0838"; ROM(3)<=X"1000" ROM(4)<=X"0017" ROM(5)<=X"0217" ROM(6)<=X"04" & '0' & vol(6 downto 0); ROM(7)<=X"06" & '0' & vol(6 downto 0); ---------------------------------------- Also, how would the following part convert, am I doing it right? VERILOG: wire GO =((address <= `rom_size) && (END==1))? COUNTER_500[10]:1; always @(negedge RESET or posedge END) begin if (!RESET) address=0; else if (address <= `rom_size) address=address+1; VHDL: process(clk) begin if rising_edge(clk) then if reset = '1' then address <= '0'; elsif address <=rom_size; end if; - Altera_Forum
"if (address <= `rom_size) address=address+1;"
I consider this sentence as that address plus one only when value of address less than or eq. to the value of rom_size. Not actualy a non-blocking assignment. Except this point, I think you translate well. P.S. I'm not a professional HDL writer. XD - Altera_Forum
And the original verilog implemented in some asynchronous approach.
verilog:always @(negedge RESET or posedge END) begin your VHDL: process(clk) begin If you want to synchronize with 'clk', it would be better to sample the 'END' signal first, and then you could finish the remaining part by using the sampled signal.
