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Altera_Forum
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15 years ago

Verilog Program - Need help with it

Hello all, I have no clue about Verilog and I want to understand a bit of program that might be useful to me. Would you happen to know what this means? I am trying to convert that into VHDL. I gue...
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Altera_Forum
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15 years ago

CLOCK_2 is a half frequency CLOCK.

GO is the 1/2048 frequency CLOCK when END is high and address is in desired region. Else , GO is high.

When END assert, the ROM read out its next data to DATA[15:0] port.

The DATA[23:16] stuck at 8'h34.

And the ROM initial value is:

ROM[0]= 16'h0c00; //power down

ROM[1]= 16'h0ec2; //master

ROM[2]= 16'h0838; //sound select

ROM[3]= 16'h1000; //mclk

ROM[4]= 16'h0017; //

ROM[5]= 16'h0217; //

ROM[6]= {8'h04,1'b0,vol[6:0]}; //

ROM[7]= {8'h06,1'b0,vol[6:0]}; //sound vol