Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Verilog Program - Need help with it

Hello all, I have no clue about Verilog and I want to understand a bit of program that might be useful to me. Would you happen to know what this means? I am trying to convert that into VHDL. I gue...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

And the original verilog implemented in some asynchronous approach.

verilog:always @(negedge RESET or posedge END) begin

your VHDL: process(clk) begin

If you want to synchronize with 'clk', it would be better to sample the 'END' signal first, and then you could finish the remaining part by using the sampled signal.