Verilog Program - Need help with it

So, would that part translate to:

signal ROM : rom_type;

After the begin of architecture

ROM(0)<=X"0c00";

ROM(1)<=X"0ec2";

ROM(2)<=X"0838";

ROM(3)<=X"1000"

ROM(4)<=X"0017"

ROM(5)<=X"0217"

ROM(6)<=X"04" & '0' & vol(6 downto 0);

ROM(7)<=X"06" & '0' & vol(6 downto 0);

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Also, how would the following part convert, am I doing it right?

VERILOG:

wire GO =((address <= `rom_size) && (END==1))? COUNTER_500[10]:1;

always @(negedge RESET or posedge END) begin

if (!RESET) address=0;

else

if (address <= `rom_size) address=address+1;

VHDL:

process(clk) begin

if rising_edge(clk) then

if reset = '1' then

address <= '0';

elsif

address <=rom_size;

end if;