Variable Precision DSP in Arria V Devices

Most designers use this hardware features by just writing behavioral code and let the design compiler choose the hardware appropriately. If you prefer structural design, look for the respective arithmetic MegaFunctions.

It's rarely required or even helpful to instantiate arithmetic hardware using low level primitives.

Why cant you just do the add in the FPGA logic?

Even better, just infer the logic from HDL code.

*edit* actually, you can just pass C into the LOADCONST port.

http://www.altera.co.uk/literature/hb/arria-v/av_52003.pdf

If you really wanted to do in inside the DSP block, you could use the 2nd multiplier input with values C and 1.

hey Tricky,

Thanks for reply. But if I add outside the following problems will come.

1) it will take extra LUTs

2) it may reduce frequency as we are not sure where it will place this logic. it may take luts for routing also. Instead if I can infer directly I can use dedicated routing for dsps which may increase overall freq.

As u said second solution : ( a x b + c x 1) It takes 2 dsps for multiplication, which increase overall dsps.

I tried even inferring with my logic like

d <= a x b;

out <= d+c;

In this case also also it's taking extra logic for adder.

One-way If i code directly out <= (a x b) + c it's inferring as varible dsps but i want multiplier put to be registered.

hey FvM,

I looked into arithmetic megafuctions. I found ALTERA_MULT_ADD, but it can do operations like a x b or (a+b) x c (it can do 4 multiplications). Preadder it can do but not (a x b) + c.

Thanks.

Nowadays (and has been the case for at least the last 10 years since Ive been in the industry) LUT usage is really not a problem. The bottleneck is usually the RAM or DSP usage. So using luts for an adder is really not a problem.

Also, with good pipelined design, in things like the stratix 4, acheiving 300MHz + is not a problem.

So the question is - what is your target device?

for easy implementation - why not go with the following code? it will infer a multiplier and an adder and should give a high fmax:

signal a,b,c    : unsigned(17 downto 0);
signal mult_out : unsigned(35 downto 0);
signal out : unsigned(36 downto 0);
process(clk)
begin
  if rising_edge(clk) then
    mult_out <= a * b;
    out <= mult_out + c;
  end if;
end process;

Hey Tricky,

You are right, now days every device has many luts. it's not a problem to use luts for adder.But module which m porting is instantiated some 70 times, in that if i take 50 luts for this module(adder logic outside) it will results in 3500 luts approximately.which is a huge number. so to avoid this, m trying to infer dsp so that my design will be optimized.

I am targeting arria v devicce.

I implemented same way in verilog and synthesized in Quartus II 14.0 (trial version). But it's inferring adder with extra logic only.

Thanks.

--- Quote Start ---

Hey Tricky,

You are right, now days every device has many luts. it's not a problem to use luts for adder.But module which m porting is instantiated some 70 times, in that if i take 50 luts for this module(adder logic outside) it will results in 3500 luts approximately.which is a huge number. so to avoid this, m trying to infer dsp so that my design will be optimized.

I am targeting arria v devicce.

I implemented same way in verilog and synthesized in Quartus II 14.0 (trial version). But it's inferring adder with extra logic only.

Thanks.

--- Quote End ---

xilinx has that sort of dsp blocks but altera doesn't though some blocks contain adders such as those for complex mult.

try set your multilipcation as axb + cx1 to use them if available in your device

Hey Tricky,

yeah, xilinix has DSP48E1 whcich can do complex operations like (a x b) + c.

Altera say they have this kind of dsp ( Variable Precision DSP in Arria V Devices ).

http://www.altera.co.uk/literature/hb/arria-v/av_52003.pdf.

But don't know how to use them / infer them.

I can do (a x b) + (c x 1) but which takes 2 dsps. Than 2 dsps going for luts is best option i think.

Thanks.

hey tricky,

Thanks. yeah as u said xilinx has DSP48e1 to do all complex functions. But altera also as similar primitive

http://www.altera.co.uk/literature/hb/arria-v/av_52003.pdf which can do similar operations ( Variable Precision DSP in Arria V Devices). But don't know how to use it / infer it.

If i use (a x b) + (c x 1) it takes 2 dsps. than 2dsps extra luts are better i think.

I gave you the code to infer them already.

I suggest reading the VHDL coding guidelines for inference.

http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf