Variable Precision DSP in Arria V Devices

Nowadays (and has been the case for at least the last 10 years since Ive been in the industry) LUT usage is really not a problem. The bottleneck is usually the RAM or DSP usage. So using luts for an adder is really not a problem.

Also, with good pipelined design, in things like the stratix 4, acheiving 300MHz + is not a problem.

So the question is - what is your target device?

for easy implementation - why not go with the following code? it will infer a multiplier and an adder and should give a high fmax:

signal a,b,c    : unsigned(17 downto 0);
signal mult_out : unsigned(35 downto 0);
signal out : unsigned(36 downto 0);
process(clk)
begin
  if rising_edge(clk) then
    mult_out <= a * b;
    out <= mult_out + c;
  end if;
end process;