Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHey Tricky,
You are right, now days every device has many luts. it's not a problem to use luts for adder.But module which m porting is instantiated some 70 times, in that if i take 50 luts for this module(adder logic outside) it will results in 3500 luts approximately.which is a huge number. so to avoid this, m trying to infer dsp so that my design will be optimized. I am targeting arria v devicce. I implemented same way in verilog and synthesized in Quartus II 14.0 (trial version). But it's inferring adder with extra logic only. Thanks.