tristate slave component

You can create an avalon tristate interface without specifying a HDL file, and there is no need for external signals.

It is enough to place avalon bus signals (clk, chipselect, address, data, read, write). The signals should be specified as input output or bidirectional. I do not know which signals should have which direction, but you should get an error if you do it wrong. In this case all the signals with the exception of clk should be placed on the SOPC symbol.

IzI

But sometimes it would be very nice to know how to setup an tristate slave with hdl ...

i wish i had a doc that describes this.

avalon tristate (and external signals) <-> verilog source

reason : i wish i could modify the always read 32bit to an external 8bit device with only the requestes bytes to be read.

my only solutions is a complete sopc module, but i have not succeded in a tri state slave. avalon <-> verilog <-> external signals

mysupport even too was not able to give me such a doc :-(

Michael

The (avalon <-> verilog) part can not use tristate signals, since there are no tristate buses in most FPGA chips. If you do use tristate signals, the wired-bus will be transformed into a multiplexer by the compiler.

So you should connect the avalon signals writedata and readdata to your verilog component, and than code them in verilog into a tristate bus (to be exported). This way you create your own avalon_tristate_bridge instead using the one provided by Altera.

NOTE: most simple component interfaces (even tristate) can be created without any HDL code, just by using the desired avalon signals. For tristate interfaces you need the avalon_tristate_bridge that is already present in SOPC builder.

In a tread about two weeks ago I posted links to Altera documentation on the subject, there is even a video.

IzI