tristate slave component

The (avalon <-> verilog) part can not use tristate signals, since there are no tristate buses in most FPGA chips. If you do use tristate signals, the wired-bus will be transformed into a multiplexer by the compiler.

So you should connect the avalon signals writedata and readdata to your verilog component, and than code them in verilog into a tristate bus (to be exported). This way you create your own avalon_tristate_bridge instead using the one provided by Altera.

NOTE: most simple component interfaces (even tristate) can be created without any HDL code, just by using the desired avalon signals. For tristate interfaces you need the avalon_tristate_bridge that is already present in SOPC builder.

In a tread about two weeks ago I posted links to Altera documentation on the subject, there is even a video.

IzI