Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

There are no Nios II CPUs with debug modules available

Hi,

I am facing this problem for over a week now, where when i try to debug as nios hardware the following error message shows up:

There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary.

just to be clear:

i have downloaded the respective .sof file (with jtag uart, and a level 1 debug module enable) to the target board (cyclone 3 running at 80Mhz external clock).

the NIOS 2 processor has on-board ram, interval timer, PIO and a jtag uart.

the clock pin on the processor is directly attached to the 80Mhz external clock pin input, and the reset pin is connected to Vcc.

here is the HW configuration:

Target Connection:

JTAG cable:

automatic<currently: USB-Blaster [USB-0]>

JTAG device:

automatic<the device which has the processor>

Nios II Terminal commnuication device:

jtag_uart_0<stdin/stdout/stderr>

https://www.alteraforum.com/forum/attachment.php?attachmentid=7361

here is a screen shot of the processor:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7362

with jtagconfig -n i got this:

[NiosII EDS]$ jtagconfig -n

1) USB-Blaster [USB-0]

020F30DD EP3C25/EP4CE22

Node 19104602

Node 0C006E02

Please advice.

Thanks.

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Is your processor running?

    Try to setup the NIOSII Hello World example and bring it to the board, if no answer comes, then your NIOS Config is not working...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    And it works with "run as", but not with "debug as", or it does not work with both?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    both run as and debug as are not working. How do i ensure the processor is running ?

    There are only two pin from the processor to connect which is the reset and clk pin, the reset is connected to vcc and the clk is connected to the external clk which is 80Mhz. (7W-80.000MBB-T as the oscillator)

    is there any other things i miss ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    both run as and debug as are not working. How do i ensure the processor is running ?

    There are only two pin from the processor to connect which is the reset and clk pin, the reset is connected to vcc and the clk is connected to the external clk which is 80Mhz. (7W-80.000MBB-T as the oscillator)

    is there any other things i miss ?

    --- Quote End ---

    this should be the mistake.

    Your CPU is in reset all the time if you put vcc to the reset!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Have you made the Tutorial for the NIOSII on your board?

    I would try this, because now there are to many things that could be. if your reset is OK now?!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Before trying on my hardware, I have tried with the de2 board and it worked, and I have been following the same steps and I still get this error.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    this should be the mistake.

    Your CPU is in reset all the time if you put vcc to the reset!

    --- Quote End ---

    Actually no. For an unknown reason, usually the reset input to a SOPC system is inverted, as shown by the name reset_n, so connecting it to vcc is the correct thing to do.

    htio, are you sure you are using the correct .sof file? Don't forget that if you are in opencore evaluation mode, the result of the compiler will be written to a *_time_limited.sof file and not the usual one.

    Did the .sof upload occur without any error? Are you sure the FPGA isn't reset (failure in a power supply for example) and reloads another design from flash?