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this should be the mistake.
Your CPU is in reset all the time if you put vcc to the reset!
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Actually no. For an unknown reason, usually the reset input to a SOPC system is inverted, as shown by the name reset_n, so connecting it to vcc is the correct thing to do.
htio, are you sure you are using the correct .sof file? Don't forget that if you are in opencore evaluation mode, the result of the compiler will be written to a *_time_limited.sof file and not the usual one.
Did the .sof upload occur without any error? Are you sure the FPGA isn't reset (failure in a power supply for example) and reloads another design from flash?
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