Honored Contributorsls provides the reference design for niosII system which includes the sram,sdram and flash.
In the design ,the clk frequence of sdram is generated by a pll. But the clk frequency is only up to 48Mhz,and the sdram IS42S16400 requires the fequency up to 166.143 MHz. Will anyone give me the explanation,please?
Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- IS42S16400 requires the fequency up to 166.143 MHz.[/b] --- Quote End --- Not "requires" but "recommends". The sdram has a minimal frequency, such as 20MHz... Take a look at the datasheet of IS42S16400.Honored ContributorThanks.
166Mhz is the frequency the datasheet recommend. But when the CLK frequency is set to 96Mhz or 160Mhz, the NiosII system can not work. Is there any restrict for frequency between sdram and Nios? By the way ,in the PLL setting ,the phase is set to -60.75 degree.why? Regards.Honored ContributorThe phase offset is there due to the board-level delays to the SDRAM, though it should be a time (in ns), rather than a phase offset. If I were you, I would:
1. Find a frequency where the SDRAM functions. - Really test the crap out of the SDRAM to do this... - Use the memtest software example/template on a design containing a DMA that is hooked up to your SDRAM and your "program" memory. 2. Translate the phase offset to a time (in ns) value. 3. Try running this design at differing frequencies to see the MAX/MIN thresholds for this setting. In reality, these are the sorts of questions you should be asking of SLS. Presumably, they tested the design(s) that they shipped with the board and have knowledge of the limits.... Cheers, - slackerHonored ContributorThe PLL's phase offset will have to be adjusted for your board; you'll probably need to look at timings with either a scope or logic analyzer. On my design, the phase offset wound up being 0; the SDRAM is right next to the Cyclone.
You should double-check the timings you gave the SDRAM component in the SOPC Builder. You may need to decrease the refresh interval if you decrease the SDRAM clock rate. Our system has a PC133 SO-DIMM (128MB, one bank) hooked up to the standard SDRAM controller. Timings are hardcoded into the SDRAM controller; it's not smart enough to configure itself from the SODIMM's Serial ROM. Even though the memory is 133 MHz, We're running it at 64 MHz with no problems. That said, I've never seen an SDRAM that ran at 166 MHz; I have seen DDR SDRAMs that use that clock frequency. The SDRAM component in Nios can't drive those; you'll need to use the Altera DDR component (but since you're running at 48 MHz, I'm not sure it's worth the bother; it's not like you're going to be able to use all that bandwidth).Honored ContributorThanks for your reply!
