the sls_sdram_controller

The PLL's phase offset will have to be adjusted for your board; you'll probably need to look at timings with either a scope or logic analyzer. On my design, the phase offset wound up being 0; the SDRAM is right next to the Cyclone.

You should double-check the timings you gave the SDRAM component in the SOPC Builder. You may need to decrease the refresh interval if you decrease the SDRAM clock rate.

Our system has a PC133 SO-DIMM (128MB, one bank) hooked up to the standard SDRAM controller. Timings are hardcoded into the SDRAM controller; it's not smart enough to configure itself from the SODIMM's Serial ROM. Even though the memory is 133 MHz, We're running it at 64 MHz with no problems.

That said, I've never seen an SDRAM that ran at 166 MHz; I have seen DDR SDRAMs that use that clock frequency. The SDRAM component in Nios can't drive those; you'll need to use the Altera DDR component (but since you're running at 48 MHz, I'm not sure it's worth the bother; it's not like you're going to be able to use all that bandwidth).