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Altera_Forum
Honored Contributor
Honored Contributorthe sls_sdram_controller
sls provides the reference design for niosII system which includes the sram,sdram and flash. In the design ,the clk frequence of sdram is generated by a pll. But the clk frequency is only up to 4...
Altera_ForumHonored Contributor
Honored ContributorThanks.
166Mhz is the frequency the datasheet recommend. But when the CLK frequency is set to 96Mhz or 160Mhz, the NiosII system can not work. Is there any restrict for frequency between sdram and Nios? By the way ,in the PLL setting ,the phase is set to -60.75 degree.why? Regards.
