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Altera_Forum's avatar
Altera_Forum
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20 years ago

the sls_sdram_controller

sls provides the reference design for niosII system which includes the sram,sdram and flash. In the design ,the clk frequence of sdram is generated by a pll. But the clk frequency is only up to 4...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

The phase offset is there due to the board-level delays to the SDRAM, though it should be a time (in ns), rather than a phase offset. If I were you, I would:

1. Find a frequency where the SDRAM functions.

- Really test the crap out of the SDRAM to do this...

- Use the memtest software example/template on a design containing a DMA that is hooked up to your SDRAM and your "program" memory.

2. Translate the phase offset to a time (in ns) value.

3. Try running this design at differing frequencies to see the MAX/MIN thresholds for this setting.

In reality, these are the sorts of questions you should be asking of SLS. Presumably, they tested the design(s) that they shipped with the board and have knowledge of the limits....

Cheers,

- slacker