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Honored Contributor
Honored Contributorthe sls_sdram_controller
sls provides the reference design for niosII system which includes the sram,sdram and flash. In the design ,the clk frequence of sdram is generated by a pll. But the clk frequency is only up to 4...
Altera_ForumHonored Contributor
Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- IS42S16400 requires the fequency up to 166.143 MHz.[/b] --- Quote End --- Not "requires" but "recommends". The sdram has a minimal frequency, such as 20MHz... Take a look at the datasheet of IS42S16400.
