the problem about multi-core CPU

Hi,

... in brief:

yes, it is possible to use designs with multiple Nios II CPUs. And it is possible to handle data sharing between the CPUs trasparently without changing too much the source code of your application. It is also possible to choose the partitioning of the tasks on the CPUs during the development cycle of your application -without- changing the hardware design, and without a great impact on the application source code (in many cases you do not need to chande the code at all).

To do that, you need some hardware and some software support... If you are looking for a demo and some documentation that explains how that can be done, try the 2-CPU demo we released at the following address: http://www.evidence.eu.com/nios2 (http://www.evidence.eu.com/nios2).

--- Quote Start ---

originally posted by lucky@Nov 7 2005, 10:06 AM

1 have you used the multi-core cpu in the pfga ? when i used the multi-

core cpu ,i had some problem about it . i had used the mailbox for the my

multi-core cpu design. i found the mailbox is equality to the two mutexs,

and then , when i one cpu read the address and the other cpu write the

same address at the same time . whether or not can the mailbox protect

the address and harmonize the two cpu to run right . if the mailbox can

not protect the address , and then how to protect the address by the

software ?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10814)

--- quote end ---

--- Quote End ---

Yes, the mailbox is basically equal to two mutexes. The usage of a mailbox is useful when you know the pattern of communication between the two CPUs.

However we think that when you developing your application, it is probably better to focus on the relationships between the various tasks in the system, and in particular the focus should be on the behavior implemented by each task, and on how each behavior implemented by a task should communicate.

Then, you should be able to partition the tasks to the various CPUs and the source code should automatically remap to multiprocessor things like mutual exclusion, cache disabling (because Nios II does not have a cache coerency hardware), and task activation.

To that extent, using Mailbozes tend to fix the data pattern you are using in the hardware design, that is fine if you know exactly what each task that is mapped to a particular CPU does, but it is not perfect if you are developing an application and you are only guessing

- how many CPUs you need to do your job

- how many task you need

- which functionality you need to put on each task

- to wich CPU each task should be partitioned

If you look at the demo I cited before, you can define a multiprocessor global data structure that is designed to be shared among -tasks- (note: not CPUs); then, depending on the partitioning you choose on the hardware, the mutual exclusion mechanism will use scheduling techniques that are local to the CPU (if all the task are allocated to the same CPU) or that are shared among the various CPUs (and in that case the RTOS will automatically use an underlying Altera Mutex to do the Job; moreover, cache disabling will be automatically enabled). All that without changing your source code :-)

--- Quote Start ---

originally posted by lucky@Nov 7 2005, 10:06 AM

2 when use the multi-core cpu, how to programme the bootloader for the

multi-core cpu? in the sopc builder , the each cpu have the respective

software system for itself. the each cpu reset from the 0x00 address,

however, the shared flash has one ox00 address . and then, how to i will

plan flash for the multi-core cpu ?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10814)

--- quote end ---

--- Quote End ---

The CPUs reset addresses should not be -all- at address 0x0, but a different addesses. Take a look at the Multiprocessor Tutorial from Altera (on the Altera web page), or to the ERIKA Enterprise documenation at the following address: http://www.evidence.eu.com/nios2/literature.asp (http://www.evidence.eu.com/nios2/literature.asp).

They explain in detail how to obtain a working multiprocessor system...

bye

Paolo

hi,Paolo

thank you for your help. I have looked at the paper you said, but i think you maybe misunderstand my meaning. In the paper you said, the ERIKA Enterprise utilized the MUTEX in their design, which is no problem. however, if the ERIKA Enterprise utilized the MAILBOX in their design, i think which mayber have some problem.

since :

1 mutex can only allow one CPU to operate the shared memory (including read and write),but, only one CPU can read or write the shared memory at the same time by binary semaphores. it is no problem to the shared memory.

mailbox is basically equal to two mutex. one mutex can only allow one CPU to read the shared memory, and the other mutex can only allow one CPU to write the shared memory. In fact, mailbox is equal to allow two CPU to operate the shared memory at the same time. therefore, the operation confusion maybe appear to same address at the same time.

for example : the digital collecting and analysing instrument have two task, one task which use one CPU to do collecting work will write data from A/D tranlator to shared memory whose address is 0xc0000000, the other task which use the other CPU to do analysing work will read data from the address is 0xc0000000 to the CPU. if two tasks will run at the same time, the operation confusion problem will turn forth about the 0xc0000000 address. therefor, i think mailbox maybe have some problem to protect the address. probably, we can use some software to solve the problem by mutual

excluding mechanism .

2 seem, there have some problem in the software about startup barrier when resets the multi-core CPU.

Hi,

--- Quote Start ---

originally posted by lucky@Nov 8 2005, 06:09 AM

in the paper you said, the erika enterprise utilized the mutex in their design, which is no problem. however, if the erika enterprise utilized the mailbox in their design, i think which mayber have some problem.

since :

1 mutex can only allow one cpu to operate the shared memory (including read and write),but, only one cpu can read or write the shared memory at the same time by binary semaphores. it is no problem to the shared memory.

mailbox is basically equal to two mutex. one mutex can only allow one cpu to read the shared memory, and the other mutex can only allow one cpu to write the shared memory. in fact, mailbox is equal to allow two cpu to operate the shared memory at the same time. therefore, the operation confusion maybe appear to same address at the same time.

for example : the digital collecting and analysing instrument have two task, one task which use one cpu to do collecting work will write data from a/d tranlator to shared memory whose address is 0xc0000000, the other task which use the other cpu to do analysing work will read data from the address is 0xc0000000 to the cpu. if two tasks will run at the same time, the operation confusion problem will turn forth about the 0xc0000000 address. therefor, i think mailbox maybe have some problem to protect the address. probably, we can use some software to solve the problem by mutual

excluding mechanism .

--- Quote End ---

About the mailbox not working when one CPU wants to write from an address and another wants to read the same address: I think there should be no problem, because the altera_avalon_mailbox_pend is a blocking call that only returns when there is data to read, whereas altera_avalon_mailbox_get is a non-blocking primitive that will return EWOULDBLOCK if there is no data to read.

About ERIKA Enterprise and the mailbox:

The idea is that using ERIKA Enterprise there is no real need to use a mailbox, because a mailbox:

- tends to impose a fixed assignment between "who reads" and "who writes" (the mailbox is needed only on a multiprocessor system, and you probably need to change your hardware and application structure if you want to change it, e.g. moving the two tasks to the same CPU to reduce costs)

- requires to manually specify the mailbox addresses (this can require some effort and bookeeping if you have a lot of mailboxes)

The ideal scenario is that users should be able to write the code in a way as much independent as possible from the CPU that will execute it, without taking care of allocations of memory regions and so on (the linker should do the job).

I perfectly understand that the last statement is kind of fuzzy; for that reason, I&#39;ll prepare a small example that implements a FIFO queue without requiring any bookkeeping. I&#39;ll post a message again on this thread when it will be ready.

--- Quote Start ---

originally posted by lucky@Nov 8 2005, 06:09 AM

2 seem, there have some problem in the software about startup barrier when resets the multi-core cpu.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10833)

--- quote end ---

--- Quote End ---

Can you be more specific about the issue you had?

In general, there are some aspects that have to be set up when using the startup barrier, in particular:

- the mutex should be configured to have an initialization value that is different from 0

- the debugger does not reset the Altera mutex when the debugger start a new program... That means the FPGA have to be reprogrammed each time you want to restart debugging the system

- to start an application, you have to start -all- the CPU, that will block at the StartOS() primitive. When all CPUs reach the StartOS primitive,all the CPU will unblock.

As the last thing, the next version of ERIKA Enterprise (planned in around 2 weeks) will have the startup barrier separate from the StartOS primitive as well as the support for Nios II 5.1.

bye

Paolo

hi, thank for your explain about mutil-core CPU.

we know mutex appear in the quartusii4.2, but mailbox appear in the quartusii5.0 and later. i think the altera&#39;s idea is to improve the efficiency about the multi-core CPU operating the shared memory. therefore, we shall try our best to use the mailbox.

1 i have had a looked the <Altera Embedded Peripherals Handbook_v5> and <Creating Multiprocessor Nios II Systems Tutorial>, but, i can not find the explicit explain about mailbox how to avoid operation confusion to the same between multi-core CPU. since, i always worry about the problem. i think that only "altera_avalon_mailbox_pend" can not account for the problem. "altera_avalon_mailbox_pend" is only a function we can call. we do not know how to design the hardware in the mailbox. therefor, i only doubt the problem, and i can not sure the problem exist, but i can also not deny the problem do exist.

2 ERIKA Enterprise use the mutex in its design. the software is based upon the mutex which control CPUs to the one and only. it is right when the multi-core resets. but, if ERIKA Enterprise use the mailbox in its design when the multi-core resets, there maybe some problem about CPUs initialization early or late. since, mailbox can not control CPUs to the one and only to access. this is only the guess.

Hi,

--- Quote Start ---

originally posted by lucky@Nov 8 2005, 03:24 PM

1 i have had a looked the <altera embedded peripherals handbook_v5> and <creating multiprocessor nios ii systems tutorial>, but, i can not find the explicit explain about mailbox how to avoid operation confusion to the same between multi-core cpu. since, i always worry about the problem. i think that only "altera_avalon_mailbox_pend" can not account for the problem. "altera_avalon_mailbox_pend" is only a function we can call. we do not know how to design the hardware in the mailbox. therefor, i only doubt the problem, and i can not sure the problem exist, but i can also not deny the problem do exist.

--- Quote End ---

I do not see big concurrency problems in using the Altera Mailbox. It&#39;s a quite simple hardware (basically a concatenation of 2 mutexes), and if you look at the HAL C source code the routines are quite simple too.

The only point where there may be race conditions is when they update the read and write pointers, but in general supposing a 32 bit bus width the write accesses are done in an atomic way by the Avalon Bus so there should be no problem...

Another point is whether to use it or not. IMHO although for small designs it is for sure a good solution, in general the solution does not scale to larger designs because it forces the modification of the hardware and of the software to modify the message passing structure of the application, and forces the manual accounting for the mailbox space...

--- Quote Start ---

originally posted by lucky@Nov 8 2005, 03:24 PM

2 erika enterprise use the mutex in its design. the software is based upon the mutex which control cpus to the one and only. it is right when the multi-core resets. but, if erika enterprise use the mailbox in its design when the multi-core resets, there maybe some problem about cpus initialization early or late. since, mailbox can not control cpus to the one and only to access. this is only the guess.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10849)

--- quote end ---

--- Quote End ---

Sorry but I did not understand the statement...

We propose the usage of a single Altera Mutex, which is used only when needed (that is, when multiprocessor issues comes in the game). Its usage is hided to the programmer, that only have to think at the functionality that have to be implemented. The code generator and the kernel code will take care of the rest.

Just to give you an idea of what I mean, I wrote a simple FIFO message passing demo (you can download it at http://www.evidence.eu.com/nios2/literature.asp (http://www.evidence.eu.com/nios2/literature.asp)). If you try it, you will find that in the demo there is no need to take care of which CPU the tasks using the FIFO are allocated to (you can even move tasks around the various CPUs without changing the code), and there is no need to account for the space allocated to the Mailbox data (the code configurator will take care of the allocation of the data and of the cache disabling for -all- the access to the shared data structure).

bye

Paolo

hi, thank for your endurant reply.

but,i always feel the mailbox has some problem in the multi-core CPU.

let us make a expreiment about mailbox in the multi-core CPU. do you like

it. we can use the two CPU to operate the address at the same which is

the address in the flash ,not in the sdram, which can increase the delay

tiem. the first, we write the intial number in the address by 0x00000000.

the second, we use one cpu to write the address by the number 0x11111111,

and use the other cpu to read the address at the same time. of course,

all of them realize by mailbox. the last, we can make a conclusion by

having a look the value from the address. right?

my ability about writing program is not well. therefore, let us write the

program together. ok? my friend. my developing board is bad and it is

repairing. it is a pity.

I think that making asmall demo with Altera Mailboxes should be not a big issue.... I think the best thing for you is to start experimenting with the Multiprocessor tutorial available from the Altera web site...

bye

Paolo

hi, thank you !

i have already made experiments about mailbox. it conclude five cpus and so many ip cores which conclude the fft, fir, noc etc. but, i always feel some problem in the mailbox because i have not written the program about it. when my developing board is repair well, i will write some experiment program to validate the mailbox. if i have some question about mailbox, i will discuss with you again.

bye

lucky

hi, Paolo

i used the demo project of evidence in the quartusii5.0 and 5.1. i can open the project, but, i can not open the the niosii processor in the SOPC BUILDER, do you know why? i want to look it.

lucky

bye

--- Quote Start ---

originally posted by lucky@Nov 12 2005, 11:34 AM

i used the demo project of evidence in the quartusii5.0 and 5.1. i can open the project, but, i can not open the the niosii processor in the sopc builder, do you know why? i want to look it.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10946)

--- quote end ---

--- Quote End ---

What is the error that SOPCBuilder is giving you?

I just downloaded the archive available on the Evidence web site to be sure.

Then,

- I decompressed the archive in c:

- I opened Quartus II 5.0 (from the about dialog box it says build 168 06/22/2005 SJ Full Version)

- then I chose "Project/Restore Archived Project...", and imported the QAR distributed inside the zip file.

- I opened the project (in my case the location is the default given by Quartus II, C:\evidence_demo_2cpu_1_1\evidence_demo_2cpu_1_1\evidence_2cpu_restored)

- and I double clicked on the SOPCBuilder icon, that opened without problems.

Please be sure to use a pathname without spaces, because SOPCBuilder refuses to open a project that has spaces inside the names...

The sequence I just described is the same described in the ERIKA Enterprise Reference Manual. The amnual in any case describes the exact sequence of steps, with screenshots, needed to reconstruct the design: for that reason, I hope there should be no problem to recreate the design for another evaluation board...

Paolo