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Ideally I would like to achieve 400 Mbps. I realize that might be unattainable or not meet timing constraints. Right now I have a 400 MHz clock coming out of a PLL and would like to output 1 bit per clock cycle (I've looked into DDR at 200 MHz but it looks like that isn't possible with VHDL/Veriliog/AHDL). I'm not sure what you mean by stopping the clock if there's no data? I was hoping to have an array and on each pos clock cycle, I would increment and output an index from the array. I'm just not sure how to get the data from my text file into an array I can access with VHDL/Verilog/AHDL.
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You need to re-phrase (or re-think) your description. What you really want is (please correct what I have stated incorrectly);
1) To generate a 400Mbps signal on an I/O pin
2) The data for that signal should come from an external SRAM
3) How do I load the data into SRAM?
Here's a few questions/answers:
1) For 400Mbps, you could use a DDR I/O pin with a 200MHz clock to the DDR I/O registers. I believe the fastest data rate for LVCMOS is around 167MHz with most devices. Your I/O options are then LVDS or one of the DDR DRAM I/O standards (SSTL, HSTL, and other funny combinations of letters). So what is it you are trying to communicate with? What output voltage swing is acceptable?
2) If the 400Mbps data is being generated using an LVDS pin, and the LVDS SERDES inside that pin is being fed at 8-bits per parallel clock, then the data rate to the SERDES is 400Mbps/8 = 50MB/s.
If your SRAM is 16-bits wide, then you need the SRAM reads to occur at a rate of 25MHz, i.e., every 40ns. This is within the capabilities of SRAM.
The IS42S16800A-7T is
sdram not SRAM
http://www.issi.com/pdf/42s16800a.pdf For that, you would need to check that burst data can be sustained to have an access time that on average is better than 40ns, eg., at 100MHz clock rate, you receive a burst of 4 words, and then no data for the next 12 clocks, i.e., your sustained rate is 4/16 * 100MHz = 25MHz. For SDRAM, you would transfer the burst to a FIFO, and the LVDS SERDES would drain the FIFO.
3) You can write to the SDRAM from your host computer. For example, if you have an Avalon-MM slave SDRAM controller, a NIOS II processor, and ethernet, you can use that to write data to SDRAM. You can also use the USB interface with a JTAG-UART to the NIOS II processor, or the JTAG-to-Avalon-MM master. You could transfer the data from SDRAM to the 400Mbps pin using a DMA master, or write your own Avalon-MM master to 'read' from the SDRAM and internally write to the FIFO, and your 400Mbps pin togging logic would read from the FIFO.
For transceiver testing I use an Avalon bus setup with pattern RAM, capture RAM, control registers, and a JTAG-to-Avalon-MM bridge. I can generate patterns across multiple 8Gbps transceiver links and capture the results to RAM, and check the results match what I expect. For these tests I use the FPGA on-chip RAM. For long patterns I use PRBS generator/checkers (they only require a few logic cells).
Cheers,
Dave
Honored Contributor
