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That's not correct. Not all the content of flash gets loaded into sram, but only what is needed or, more exactly, what is specified in the bootloader.
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Ah ok good to know, thanks.
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I don't understand what you mean when you say you want the file to be accessed from vhdl files.
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What sort of output bit rate are you after?Are you generating the clock edges as well as the data?
More particularly can you stop the clock if there is no data?
I don't how fast the EPCS memory reads actually are (is it some kind of serial protocol??), but, unless you need a very high rate I don't necessarily see the reason to copy the data to SRAM.
I think someone has done an avalon slave that will (slowly) directly read EPCS memory (some references to execution Nios code directly from EPCS), so maybe you could 'just' dma onto a parallel->serial converter.
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Ideally I would like to achieve 400 Mbps. I realize that might be unattainable or not meet timing constraints. Right now I have a 400 MHz clock coming out of a PLL and would like to output 1 bit per clock cycle (I've looked into DDR at 200 MHz but it looks like that isn't possible with VHDL/Veriliog/AHDL). I'm not sure what you mean by stopping the clock if there's no data? I was hoping to have an array and on each pos clock cycle, I would increment and output an index from the array. I'm just not sure how to get the data from my text file into an array I can access with VHDL/Verilog/AHDL.
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