Forum Discussion
Altera_Forum
Honored Contributor
14 years agoText file to Flash to VHDL
Hello, I am trying to access the contents of a text file (full of binary data) via an array in VHDL on my Cyclone II device. I would like to output one bit per clock cycle to one of my FPGA pin...
Altera_Forum
Honored Contributor
14 years agoThank you for the informative reply Dave.
I did mean SDRAM, not SRAM, it was a typo so my mistake! I would like to use my USB Blaster cable to load the file into the memory. Currently the file is in a normal text file with 1s and 0s, and I am guessing this is incorrect and needs to be changed to something else. I tried opening the nios2-terminal (I have no experience using this) but it told me there are no JTAG UARTs available which match the --device and --instance options. Perhaps the JTAG-to-Avalon-MM option would be easier. I am afraid I have little experience interacting with any of the Nios components. (I do have SDRAM Avalon MM slave and EPCS_Controller Avalon MM slave already incorporated in the Nios CPU however). If I understand one way to do implement this: 1) Format text file 2) Load into SDRAM using USB Blaster via JTAG 3) Load data from SDRAM into FIFO 4) Connect pin to read from FIFO at 400Mbps Any help or advice would be greatly appreciated. I am scouring tutorials, examples, and forum posts to figure these steps out, but I am having difficulties. Thank you