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Honored Contributor
Honored ContributorText file to Flash to VHDL
Hello, I am trying to access the contents of a text file (full of binary data) via an array in VHDL on my Cyclone II device. I would like to output one bit per clock cycle to one of my FPGA pin...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I took a short hiatus on this project but I am resuming it again this week. I found various webinars on Tcl and scripting and I've gone through them. One thing that is still unclear to me: Tcl seems to give me the tools to fill the on board memory with my data, but how do I set up the FIFO to read in at the correct rate and out to the pin? Happy holidays --- Quote End --- You write a state machine and then control registers for the state machine. For example, here's what I have for testing SERDES channels; 1) An Avalon-MM system containing a JTAG-to-Avalon-MM master, various blocks of control registers, and pattern RAM blocks. 2) The pattern RAM is dual ported; with one side having an Avalon-MM slave interface, the other side connects to the serializer state machine. 3) The serializer state machine reads a word from SRAM and writes it to the SERDES channels. This state machine is enabled via a control register bit. You could do something similar. Cheers, Dave
