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Altera_Forum
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14 years ago

Text file to Flash to VHDL

Hello, I am trying to access the contents of a text file (full of binary data) via an array in VHDL on my Cyclone II device. I would like to output one bit per clock cycle to one of my FPGA pin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

What sort of output bit rate are you after?Are you generating the clock edges as well as the data?

More particularly can you stop the clock if there is no data?

I don't how fast the EPCS memory reads actually are (is it some kind of serial protocol??), but, unless you need a very high rate I don't necessarily see the reason to copy the data to SRAM.

I think someone has done an avalon slave that will (slowly) directly read EPCS memory (some references to execution Nios code directly from EPCS), so maybe you could 'just' dma onto a parallel->serial converter.