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Altera_Forum's avatar
Altera_Forum
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20 years ago

System hangs in reset_device()

Hi,

I'm using a Stratix II development board with NIOS II 1.1 and I am trying to initialize the network interface and the lightweight IP stack as done in the web server example. The network interface is present in my SOPC design.

However, when I initialise the hardware using lwip_devices_init(PRIORITY), it hangs in reset_device(): 

12 OSIntCtxSw() at \cygdrive\c\altera\kits\nios2\components\altera_nios2\UCOSII\src\os_cpu_a.S:126
11 OS_Sched() at \cygdrive\c\altera\kits\nios2\components\micrium_uc_osii\UCOSII\src\os_core.c:1199
10 OSTimeDly() at \cygdrive\c\altera\kits\nios2\components\micrium_uc_osii\UCOSII\src\os_time.c:55
9 usleep() at \cygdrive\c\altera\kits\nios2\components\altera_nios2\UCOSII\src\alt_usleep.c:90
8 reset_device() at \cygdrive\c\altera\kits\nios2\components\altera_avalon_lan91c111\UCOSII\src\altera_avalon_lan91c111.c:466
7 low_level_init() at \cygdrive\c\altera\kits\nios2\components\altera_avalon_lan91c111\UCOSII\src\altera_avalon_lan91c111.c:753
6 alt_avalon_lan91c111_init() at \cygdrive\c\altera\kits\nios2\components\altera_avalon_lan91c111\UCOSII\src\altera_avalon_lan91c111.c:163
5 netif_add() at \cygdrive\c\altera\kits\nios2\components\altera_lwip\UCOSII\src\downloads\lwip-0.7.2\src\core\netif.c:85
4 lwip_devices_init() at \cygdrive\c\altera\kits\nios2\components\altera_lwip\UCOSII\src\alt_lwip_dev.c:135
3 init_done_func() at ..\SystemInit\Special_c_func.cc:22
2 tcpip_thread() at \cygdrive\c\altera\kits\nios2\components\altera_lwip\UCOSII\src\downloads\lwip-0.7.2\src\api\tcpip.c:92
1 OSStartTsk() at \cygdrive\c\altera\kits\nios2\components\altera_nios2\UCOSII\src\os_cpu_a.S:265

The software initialization appears to complete successfully, but I am stuck at the this point. I have been trying to give different IRQ numbers, to give different priorities to the tasks, reloading the quartus II design many times and resetting the board by taking off the power and waiting for 30 seconds.

Does anyone have an idea would could be going on?

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi jmastron,

    what hardware configuration design are u using?an example design or your own design? If it's your own, try first an example design; then, if it works, check the connections between FPGA and LAN91C111 pins, in your design.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi, I'm using a modified standard reference design. I'm quite sure the pins are connected properly, because sometimes it does work (after trying many times)

    Also, when I take the standard web server example, it also works fine.

    My design in SOPC builder contains multiple CPU's. Could this be a problem? (the MAC is only connected to one cpu)
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi jmastron,

    i'm developing a multiprocessor design too, with a processor interfacing LAN91C111. Where do your processors boot from? Do your processors share some peripherals? I had several problems in my design, so let me know more about yours, maybe i could suggest you somethngs...
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi Soin

    At the moment we start everything from the NIOS IDE, we have not flashed any of our software on the board yet. We first want to see it working http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif So we program the software trough the JTAG. The only thing the CPU&#39;s share is the SDRAM (which works fine). Any suggestions?
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi jmastron,

    so i suppose that the reset address settings in SOPC builder, of your CPUs are in SDRAM space, so they will boot undefined code...

    I suggest u to program first the processor that doesn&#39;t interface LAN, with a simple program that doesn&#39;t interfere with SDRAM space used by the other processor (if u have only 2 processors...), then program the processor that uses the LAN...
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi Soin,

    Thanks for the quick replies!

    the reset adresses of the CPU&#39;s are indeed in SDRAM space, but since the code is loaded by the JTAG there is no execution of undefined code (I hope). But since you say it might cause problems anyway, I just modified my system to use the flash for it reset address.

    As for the test with a simple program, that&#39;s what I already did: I ran the webserver example using DHCP on the CPU that interfaces the LAN. That runs fine, it can initialize the MAC and gets an IP from the DHCP server. So it the MAC part seems to be working.

    I&#39;ll post my findings here as soon as quartus and the NIOS IDE will finish compiling
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi jmastron,

    i suppose you first download FPGA configuration on the board, so the processors will start and execute undefined code from SDRAM...

    ...but do program end data memory of both processors reside in SDRAM? do both processors run from SDRAM?have u partitioned SDRAM space?
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi Soin,

    what I had was that both the program and data memory reside in partitioned sdram. I have tested this many other applications and it seems to work fine. But what you are saying is that when I download the quartus design onto the board, that the CPU&#39;s will already start to execute code? I thought they remained paused, untill you load the code into the memory with the JTAG... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Yes It is!

    So if u download a program only for a CPU, u don&#39;t know what the other CPU is running! And this could cause problems for the first CPU, if u share some resources...
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    (Quartus is still compiling)

    Then how can I load the software for all the cpus and let them start at the same time? Do I have to flash the software into the flash chip?

    Btw: the CPU&#39;s only share the SDRAM which is partioned, nothing else. So there are no simultaneous accesses on other perhiperals.

    Besides putting the reset address to flash, should I write some data in the flash as well?