Simulating Nios II in ModelSim-Altera

It's kind of klunky but the way I've done it in the past is to add external logic to the top level VHDL file generated by SOPC builder. If you look in this file, there are comment sections which look like this:

-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

--add your libraries here

-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

or

-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

--add your component and signal declaration here

-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

or

-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

--add additional architecture here

-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

If you keep the stuff you add within these ALTERA_NOTE sections, then it won&#39;t be deleted when you run SOPC builder again.

The thing I don&#39;t like about this method is that it doesn&#39;t test the actual connectivity of your fpga or board design. You have to re-enter the design in VHDL just to simulate it.

--

Terry

Hello.

A other way is to setup your own top-level simulation.

All you need is a project setup where the nios II is included as an instance. For the top-level testbench you add the external peripheral such as clock generation and input data which is needed to simulate the design.

Then add the used nios II files to your modelsim project. (You can see the needed files in the setup_sim.do file from the simulation directory of the Quartus II Project.

You will also need some hex and/or dat files. The files are located in the simulation directory of the Quartus II project or direct in the Quartus II Project directory.

The advantage of this method is that you simulate your design as you use it inside of the FPGA. But it is complex to add the nios II Signals which are inside the CPU.

So you can check the connectivity and the initialization of units which are connected to the CPU.

Hope this helps you.

MfG

Chris

Hi ecm!

Ok, thanks for the answer, something is working but not completely... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

For example, I can&#39;t simulate the jtag_uart output and I can&#39;t found my external logic signals to add in the Wave Window of ModelSim.

Probably I&#39;ve mistaken something in editing the *.do file..?!?!

Bye

Hi Matteo,

Do you use the simulation directory from Quartus II or do you use your own simulation directory outside the Quartus tree?

When you use a directory structure out of the Quartus directory you must also copy some files for the jtag_uart_log.

There are also some path-definitions in the setup.do file which are needed to log uarts.

When you use a normal uart in the project, the output will be also displayed in the modelsim window.

Do you get warnings when you compile the project in modelsim?

MfG

Chris

Thaks for your fast answer.

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Do you use the simulation directory from Quartus II or do you use your own simulation directory outside the Quartus tree?[/b]

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This is the directory in which I have my QPF QuartusII project file (standard.qpf):

C:\altera\Progetti\ProvaCpu

This is the directory auto-generated by SOPC for the ModelSim simulation in which I have my MPF file (std_1s40_sim.mpf):

C:\altera\Progetti\ProvaCpu\std_1s40_sim

This is the directory auto-generated by QuartusII in which Quartus has created the output file for ModelSim (standard.vo):

C:\altera\Progetti\ProvaCpu\simulation\modelsim

I defined my new ModelSim Project file (testbench.mpf) in this last directory, together with the other copied files (setup_sim.do, modelsim.tcl,ecc...). Of course, I have a little edited these files, but I don&#39;t know if correctly.

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Do you get warnings when you compile the project in modelsim?[/b]

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No, I don&#39;t. It seems all ok, but I have the problems I desribed in the last post. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

Bye!

Hello Matteo,

do you want to do a rtl or post-layout simulation?

The last directory (which you use) is for post-layout simulation. Quartus writes the complete project (nios + custom hdl-files) into this directory. Because of the synthesis (built in into Quartus, or with a third party tool) the signal names can change.

When you just want to make a pre-layout simulation you can use the second directory (std_1s40_sim) and change the project setup by writing your own setup-file.

MfG

Chris

Hello ecm!

I really appreciate your helpful answers.

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... the signal names can change.[/b]

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Ok, maybe this is the reason I don&#39;t apparently find my added signal in ModelSim.

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... you can use the second directory (std_1s40_sim) and change the project setup by writing your own setup-file.[/b]

--- Quote End ---

Ok, it looks like simple, but I don&#39;t know how to do this. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

Are there any tutorials? I wonder Altera doesn&#39;t provide anything about this...

Bye

Hello Matteo,

I don&#39;t know if there any tutorials provided from Altera. Maybe you can also find something in the documentation of your simulation tool. You can also try to check out a project from (opencores (http://www.opencores.org) to see how to simulate designs. Often there are also included some testbenches.

Now I will explain in a short form how to simulate a design with an embedded IP-core (such as the nios II)

first you need your own testbench where the signals are driven.

In this the top-level entity (your complete FPGA-Design) is instantiated.

Inside of your top level entity there can be on or more instances of several units. (maybe also the nios-processor)

I try to illustrate this in a tree view:

tb_top (your testbench)

- additional generators (you need to generate a clock and reset signal. Maybe you also want to simulate external units.)

- top (your fpga design)

+ unit 1 (a user defined unit)

+ unit x (there can be more user defined units)

+ nios_cpu (the nios II cpu)

for simulating you must add all files to the project (upside down, nios and units before your top, top before your tb).

The files which you need for the nios_cpu can be found in the setup_sim.do file.

MfG

Chris