Simulating Nios II in ModelSim-Altera

It's kind of klunky but the way I've done it in the past is to add external logic to the top level VHDL file generated by SOPC builder. If you look in this file, there are comment sections which look like this:

-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

--add your libraries here

-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

or

-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

--add your component and signal declaration here

-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

or

-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

--add additional architecture here

-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

If you keep the stuff you add within these ALTERA_NOTE sections, then it won&#39;t be deleted when you run SOPC builder again.

The thing I don&#39;t like about this method is that it doesn&#39;t test the actual connectivity of your fpga or board design. You have to re-enter the design in VHDL just to simulate it.

--

Terry