Forum Discussion
Altera_Forum
Honored Contributor
21 years agoHello.
A other way is to setup your own top-level simulation. All you need is a project setup where the nios II is included as an instance. For the top-level testbench you add the external peripheral such as clock generation and input data which is needed to simulate the design. Then add the used nios II files to your modelsim project. (You can see the needed files in the setup_sim.do file from the simulation directory of the Quartus II Project. You will also need some hex and/or dat files. The files are located in the simulation directory of the Quartus II project or direct in the Quartus II Project directory. The advantage of this method is that you simulate your design as you use it inside of the FPGA. But it is complex to add the nios II Signals which are inside the CPU. So you can check the connectivity and the initialization of units which are connected to the CPU. Hope this helps you. MfG Chris