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Honored Contributorsimple socket server connection established, but cannot ping/telnet
hello guys,
I got a problem with simple socket server problem. I post similiar thread in dev kit forum, but no answer until now. I am thinking maybe I could get help from here. Thank you in advance. My situation is here: hardware: cIII 120 develop board software: QII 9.1 sp2, Nios II 9.1 sp2 What i have done: 1. copy the C:\altera\91\nios2eds\examples\verilog\niosII_cycl oneIII_3c120\triple_speed_ethernet_design to my project fold and open with QII 2. open sopc builder and run generate 3. back to QII and compile to generate sof (time limited version) 4. open nios eclipse ide, create a new project with simple socket server template 5. to avoid troulbe, modife get_mac_addr() as: ****************************************** int get_mac_addr(NET net, unsigned char mac_addr[6]) { mac_addr[0]=0xB7; mac_addr[1]=0xA7; mac_addr[2]=0xED; mac_addr[3]=0xFF; mac_addr[4]=0xFF; mac_addr[5]=0xFF; return 0; // return (get_board_mac_addr(mac_addr)); } ****************************************** 6. I disable DHCP in wizard and I use cross cable to connect board and PC directly. 7. run app as "Nios II hardware" what I got: =============== Software License Reminder ================ This software project uses an unlicensed version of the NicheStack TCP/IP Network Stack - Nios II Edition. If you want to ship resulting object code in your product, you must purchase a license for this software from Altera. For information go to: "http://www.altera.com/nichestack" ================================================== === InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 Static IP Address is 192.168.1.234 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x08004000 INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 100, Duplex = Full OK, x=1, CMD_CONFIG=0x00000000 MAC post-initialization: CMD_CONFIG=0x04000203 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 192.168.1.234 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) Simple Socket Server starting up [sss_task] Simple Socket Server listening on port 30 Created "simple socket server" task (Prio: 4) Everything looks smooth, but I cannot ping, telnet or whatever else. When I ping, the RX light is flashing, but TX light not.43 Replies
Altera_ForumIf you fix your PC for 100mbps , then you must be able to send and receive data.
May be your PHY device reqiure 2.5MHz for 10mbps, 25MHz for 100mbps and 125 MHz for 1000mbps and you are providing only 25MHz. Just fix your PC for 100mbps and try then let me know.........- Altera_Forum
Try this in your client program
ConnectedToServer = False; while (!ConnectedToServer) { Create Client socket; Configure socket (address family etc...) Fill in server sock addr struct.. etc.. try Connect; If success ConnectedToServer = true; Else Close client socket; memset all structs to 0x00; Optionally add some delay; } - Altera_Forum--- Quote Start --- If you fix your PC for 100mbps , then you must be able to send and receive data. May be your PHY device reqiure 2.5MHz for 10mbps, 25MHz for 100mbps and 125 MHz for 1000mbps and you are providing only 25MHz. Just fix your PC for 100mbps and try then let me know......... --- Quote End --- Hi,rahul Thank you really much, when I fix my pc for 100Mbps and connect the board and PC with a cross-over cable. I succeed!!! But I still have a problem. As my PHY is 88E1111, so if I want to use 1000Mbps, what should I do ? Thanks for your help.
- Altera_Forum
You need to provide different clock to Marvell 88E1111 PHY Device for different speed
2.5MHz for 10mbps 25MHz for 100mbps 125MHz for 1000mbps You are able to transfer data at 100mbps because you are providing a clock of 25MHz to your PHY device - Altera_Forum
How are you connecting the PHY and the TSE? Did you put timing constraints on the I/O and does the design meet timing requirements?
- Altera_Forum--- Quote Start --- You need to provide different clock to Marvell 88E1111 PHY Device for different speed 2.5MHz for 10mbps 25MHz for 100mbps 125MHz for 1000mbps You are able to transfer data at 100mbps because you are providing a clock of 25MHz to your PHY device --- Quote End --- How can I provide 125Mhz clock to PHY Device? Should I change something in sopcbuilder or the verilog code in Top-level file? In the circuit diagram of PHY Device, I can only find ENET_25MHZ and it is give to XTAL1 in 88E1111.
- Altera_Forum--- Quote Start --- How are you connecting the PHY and the TSE? Did you put timing constraints on the I/O and does the design meet timing requirements? --- Quote End --- I connect the PHY and the TSE with .v files(top-level file?). I didn't put timing constraints on the I/O. Will it affect my project? What should I do?
- Altera_Forum--- Quote Start --- You need to provide different clock to Marvell 88E1111 PHY Device for different speed 2.5MHz for 10mbps 25MHz for 100mbps 125MHz for 1000mbps You are able to transfer data at 100mbps because you are providing a clock of 25MHz to your PHY device --- Quote End --- Under RGMII The output pin of FPGA----ENET0_GTX_CLK can provide a 125MHz/25MHz/2.5MHz reference clock. What should I do to make sure it provide 125MHz?
- Altera_Forum
hello benjaminlunsky..
will you please send your project? i have the same problem and i am not able to sort it out.. i am too working on socket programing for my kit.. - Altera_Forum--- Quote Start --- hello benjaminlunsky.. will you please send your project? i have the same problem and i am not able to sort it out.. i am too working on socket programing for my kit.. --- Quote End --- what kind of problem do u have? Could u describle it ?
