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Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- You need to provide different clock to Marvell 88E1111 PHY Device for different speed 2.5MHz for 10mbps 25MHz for 100mbps 125MHz for 1000mbps You are able to transfer data at 100mbps because you are providing a clock of 25MHz to your PHY device --- Quote End --- Under RGMII The output pin of FPGA----ENET0_GTX_CLK can provide a 125MHz/25MHz/2.5MHz reference clock. What should I do to make sure it provide 125MHz?