SDR SDRAM memory tests

Hello,

I've designed a board, with 5 separate SDR SDRAM chips, now I've got the PCBs and trying to test the memory reads/writes. 3 of the chips are working fine, however two of them behaves strange.

For memory tests, I've created a small Qsys design with on-chip memory, where I've placed Nios. The CPU runs an example of Altera called Memory test.

Now here's what's happening:

             <---->   Nios II Memory Test.   <---->
This software example tests the memory in your system to assure it
is working properly.  This test is destructive to the contents of
the memory it tests. Assure the memory being tested does not contain
the executable or data sections of this code or the exception address
of the system.
----------------------------------
      Memory Test Main Menu
----------------------------------
     a:  Test RAM
     b:  Test Flash
     q:  Exit
----------------------------------
Select Choice (a-b): 
a
Base address to start memory test: (i.e. 0x800000)
>
0x00
End Address:
>
0x7fffff
Testing RAM from 0x0 to 0x7FFFFF
 -Data bus test passed
 -Address bus test passed
 -Byte and half-word access test passed
 -Testing each bit <<-- not a full sentence, crashed here!
             <---->   Nios II Memory Test.   <---->
This software example tests the memory in your system to assure it
is working properly.  This test is destructive to the contents of
the memory it tests. Assure the memory being tested does not contain
the executable or data sections of this code or the exception address
of the system.
----------------------------------
      Memory Test Main Menu
----------------------------------
     a:  Test RAM
     b:  Test Flash
     q:  Exit
----------------------------------
Select Choice (a-b): 

As You can see, the sentence "-Testing each bit in memory device . . . ." has been cut and the software restarted. I don't understand why is this happening and what could cause such crashes. Sometimes, the data output is cut somewhere else, e.g. in the beginning of tests: "Testing RAM" and then immediate restart.

The system clock is 50MHz

The SDRAM chip is feeded 50MHz -55deg from the same PLL

I am pretty sure the connections are OK.

If I give incorrect clock to the chip, e.g. the same clock, as I give it to memory controller, then it just stops right after memory tests start, giving a result, that memory test failed at bit 0x1.