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Altera_Forum
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14 years ago

SDR SDRAM memory tests

Hello, I've designed a board, with 5 separate SDR SDRAM chips, now I've got the PCBs and trying to test the memory reads/writes. 3 of the chips are working fine, however two of them behaves strang...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Firstly I'd rewrite the JTAG? UART driver to be completely synchronous and/or add enough delay after every \n to ensure the output has drained.

Otherwise you have NFI when the lockup happens.

Make sure you have code at the reset vector that indicates a reset - not a restart etc.