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dim1
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4 hours ago

Run-time errors using EMIF in Agilex 5 NIOS-V design

Hello,

I am using Quartus Prime Pro 26.1.1, with the Agilex 5 development board (AXE5-Eagle). I am trying to run the NIOS-V code from the LPDDR4 memory, using JTAG to download/debug. The reset and exception vectors are set to the On-Chip RAM. I used the sample design provided for that board - AXE5 Eagle mipi_hdmi_mira220 and removed everything related to MIPI and HDMI. Added JTAG Uart IP. The resulting sample design is attached (mipi_hdmi_mira220.zip). In the software/ directory you can also see the FreeRTOS BSP I used.

I created a simple FreeRTOS application that just prints some string to stdout.

What I am seeing is - the RISC-V processor throws exceptions - one of the following - Misaligned Read Address, Misaligned Write Address or Invalid Instruction. This happens in alt_load_section(). If I execute step-by-step, no exception is thrown. But if I just run the application it fails.

Is there something else that need to be added/updated/changed, in order to be able and execute code from LPDDR4 using the EMIF IP?

I could not find any existing sample design, using NIOS-V and EMIF, with code execution from EMIF.

Thank you,

D.

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  • dim1's avatar
    dim1
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    I did notice that s0_axi4_ctrl_ready was not used. Attached is an updated design where the s0_axi4_ctrl_ready is connected to the NIOS-V reset, to keep NIOS-V in reset until the EMIF is ready. It did not change anything - still the same problem.