Run-time errors using EMIF in Agilex 5 NIOS-V design

Thank you for the measurements! That isolates the issue. And glad to hear it is working now!

ARSIZE=2 on every instruction fetch means the Platform Designer width converter is issuing AXI narrow reads (4-byte transfers) into the 256-bit LPDDR4 interface. On this device (A5ED065BB32AE4SR0), Fabric EMIF does not support narrow reads; it expects full-width transfers (ARSIZE=5) with addresses aligned to 32 bytes. mcause 0/2/4/6 is what you get when those reads return bad instruction or data. Reset changes cannot fix that, and Nios V/g vs V/m does not change it either — both managers are 32-bit.

That is also why the OCRAM memory test passed: instruction fetches were not going to LPDDR4. XIP puts a continuous stream of instruction reads onto that unsupported path.

You do not need to create a new IP. Address Span Extender is the supported catalog IP for connecting Nios V to EMIF, including as instruction/data memory. It is what the Agilex 5 Nios V GHRD uses. A direct Nios AXI4-Lite connection to s0_axi4 is not a reliable XIP topology here, because that path keeps ARSIZE=2.

ASE is not required in your design because the DRAM is larger than 4 GB (your LPDDR4 window already fits in the 32-bit map). It is required because it is the supported adapter that presents a 32-bit window to Nios and lets the interconnect issue legal full-width EMIF beats. There are other bridges in the catalog, but they are not the documented XIP solution and they can still pass narrow ARSIZE through. I recommend staying with ASE.

For execute-in-place, please keep: datapath 32-bit, a single sub-window, and the slave control port disabled. If you want a final check, SignalTap on s0_axi4 with ASE in place should show ARSIZE=5 and ARADDR[4:0]=0.

Thank you,
Radu