Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory to store required code. The whole system should run from altmemddr PLL. However, the EDS tool doesn't find neither sysid, nor timestamp. What is wrong with this design? I have tried to add timer, but that didn't help and afaik it is not required. DDR2 pins are OK, I have taken them from a working example from development board CD.

--- Quote Start --- DDR2 pins are OK, I have taken them from a working example from development board CD. --- Quote End --- Do you mean you tested the example on the same board? Or is this your custom board which pin locations have been copied from the dev board? I don't think the problem is with ddr, since debugging tools should be able to get the correct sysid even if memory is not working. IMHO it's more probable the Nios is not working. Maybe a problem with input clock or reset signal. Are you sure the fpga has been correctly configured? Anyway I'd suggest this simple method to exclude ddr: you can temporarily replace it with onchip memory; this is enough for a "Hello world" kiind of program and it will let you take away any concern regarding external connections.

I have replaced the DDR2 memory with on-chip memory (262144 bytes), but the issue somehow was 125MHz clock. I have set the 50MHz clock instead and the Nios started. The 125MHz clock was running for sure, I have made a blinker which works either with 125MHz clock or with 50MHz clock. The development board is Cyclone III Host board from Altera (2 clocks on board + SMA IN) Now the strange problem is that the console doesn't show anything. It runs the CPU: --- Quote Start --- Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Reading System ID at address 0x00081030: verified Initializing CPU cache (if present) OK Downloading 00040000 ( 0%) Downloading 00045CD0 (71%) Downloaded 24KB in 0.4s (60.0KB/s) Verifying 00040000 ( 0%) Verifying 00045CD0 (71%) Verified OK Starting processor at address 0x00040184 --- Quote End --- I've checked BSP parameters, the stdin/stdout/stderr are all set to uart_jtag, but the console screen is empty.

Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation. But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur.

you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection

--- Quote Start --- Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation. But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur. --- Quote End --- I will try to do that, but I've also tried to run debug. The output says, that the processor is started, but when the debug window comes up, I see the processor "terminated". I don't know why is this happening. There are 4 critical warnings because of constraints, but those are common and not familiar with Nios. Something like clock uncertainty on JTAG TCK pin, actually can't remember now the exact warning... In addition, Nios now runs on 50MHz directly from the clock, so should be fine. --- Quote Start --- you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection --- Quote End --- Yes, I know, but this is used for mismatched systems, that are familiar. E.g. You use somewhere compiled .sof file, but generate Your own Nios code. This feature doesn't work, when the core is not running. ID and timestamp fields are marked "Not found". Thanks for the help.

Required Nios components | Altera Community

47 Replies

Altera_Forum
Honored Contributor
14 years ago
I just tried running this:

int main()
{
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 \n");

return 0;
}

and got this:

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 HHllooffoo iissII!!1133557799aacceeggiikkmmooqqssuuwwyy 2244668800

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz1133557799 HHllooffoo iissII!!1133557799aacceeggiikkmmooqqssuuwwyy 2244668800

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890 HHllooffoo iissII!!1133557799aacceeggiikkmmooqqssuuwwyy 2244668800

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz1133557799 HHllooffoo iissII!!1133557799aacceeggiikkmmooqqssuuwwyy 2244668800
Altera_Forum
Honored Contributor
14 years ago
I just ran this:

int main()
{
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890123 \n");

return 0;
}
and got this:

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz 1234567890133

Notice the missing 2 and repeated 3 at the end of each line...
Altera_Forum
Honored Contributor
14 years ago
Run the whole design using only on-chip memory. That doesn't seem like frequency issue, more like RAM problems.
Altera_Forum
Honored Contributor
14 years ago
Ah ha! Problem solved (for now). I tried adding a data cache to the Nios II cpu and that fixed it. I added a tightly-coupled data master (already had a tightly-coupled instruction master) using on-chip memory.

The sample app Memory Test now works if I remove the byte/word section. I am not using the BHEn and BLEn pins on my SRAM to conserve pins, but will include them in the production version of the board. I didn't think that I would need these pins if I went with straight 16-bit accesses. Would I have had this problem if I had these lines implemented? I guess I won't know for sure until I test the next version of my board.

Anyway, many thanks to all of you who offered suggestions and insight into this issue that has been haunting me for weeks.
Altera_Forum
Honored Contributor
14 years ago
The data cache will mask those problems because it will always do 32-bit accesses. Without the cache (or if you do an access by bypassing the cache) all 8-bit writes will fail. I guess that 8-bit accesses can happen in I/O functions, but also possibly in all string-manipulating functions, so it could be a problem.
According to this message by dsl (http://www.alteraforum.com/forum/showpost.php?p=123683&postcount=4), you will also run into problems with 16-bit accesses if you don't connect the byte enable lines, so you should keep the data cache for now, and avoid any cache bypassing.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
The data cache will mask those problems because it will always do 32-bit accesses. Without the cache (or if you do an access by bypassing the cache) all 8-bit writes will fail. I guess that 8-bit accesses can happen in I/O functions, but also possibly in all string-manipulating functions, so it could be a problem.
According to this message by dsl (http://www.alteraforum.com/forum/showpost.php?p=123683&postcount=4), you will also run into problems with 16-bit accesses if you don't connect the byte enable lines, so you should keep the data cache for now, and avoid any cache bypassing.
--- Quote End ---

I noticed when setting up the Nios II data cache in Qsys that we have a choice of "Data cache line size". I first tried setting it up as 16-bit and it worked. Then I changed it to 32-bit to see what would happen, and it still worked. Would it be best if I set it for 16-bit and enable burst transfers?
Altera_Forum
Honored Contributor
14 years ago
Those cache line sizes should be in bytes.
Altera_Forum
Honored Contributor
14 years ago
The memory interface might behave differently from the normal bus width adapter that SOPC adds for you.
We certainly saw the PCIe slave bridge doing two 32bit transfers (one with no byte enables) when the external PCIe master requested a 32bit transfer.
Altera_Forum
Honored Contributor
14 years ago
sorry...missed that I was only on page one when I posted quick reply...nothing to see here, keep moving!
Altera_Forum
Honored Contributor
14 years ago
Burst transfers shouldn't make a big difference on an SRAM. As for the cache line size, as dsl says the size is in bytes and not bits. Each time a transfer is required between the cache and the main memory, a full line will be read/written. Whether 16 or 32 is better depends a lot on the application (both hardware and software). You can try both and see if one performs better than the other on your system.

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