Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Required Nios components

Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ah ha! Problem solved (for now). I tried adding a data cache to the Nios II cpu and that fixed it. I added a tightly-coupled data master (already had a tightly-coupled instruction master) using on-chip memory.

The sample app Memory Test now works if I remove the byte/word section. I am not using the BHEn and BLEn pins on my SRAM to conserve pins, but will include them in the production version of the board. I didn't think that I would need these pins if I went with straight 16-bit accesses. Would I have had this problem if I had these lines implemented? I guess I won't know for sure until I test the next version of my board.

Anyway, many thanks to all of you who offered suggestions and insight into this issue that has been haunting me for weeks.