Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory to store required code. The whole system should run from altmemddr PLL. However, the EDS tool doesn't find neither sysid, nor timestamp. What is wrong with this design? I have tried to add timer, but that didn't help and afaik it is not required. DDR2 pins are OK, I have taken them from a working example from development board CD.

--- Quote Start --- DDR2 pins are OK, I have taken them from a working example from development board CD. --- Quote End --- Do you mean you tested the example on the same board? Or is this your custom board which pin locations have been copied from the dev board? I don't think the problem is with ddr, since debugging tools should be able to get the correct sysid even if memory is not working. IMHO it's more probable the Nios is not working. Maybe a problem with input clock or reset signal. Are you sure the fpga has been correctly configured? Anyway I'd suggest this simple method to exclude ddr: you can temporarily replace it with onchip memory; this is enough for a "Hello world" kiind of program and it will let you take away any concern regarding external connections.

I have replaced the DDR2 memory with on-chip memory (262144 bytes), but the issue somehow was 125MHz clock. I have set the 50MHz clock instead and the Nios started. The 125MHz clock was running for sure, I have made a blinker which works either with 125MHz clock or with 50MHz clock. The development board is Cyclone III Host board from Altera (2 clocks on board + SMA IN) Now the strange problem is that the console doesn't show anything. It runs the CPU: --- Quote Start --- Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Reading System ID at address 0x00081030: verified Initializing CPU cache (if present) OK Downloading 00040000 ( 0%) Downloading 00045CD0 (71%) Downloaded 24KB in 0.4s (60.0KB/s) Verifying 00040000 ( 0%) Verifying 00045CD0 (71%) Verified OK Starting processor at address 0x00040184 --- Quote End --- I've checked BSP parameters, the stdin/stdout/stderr are all set to uart_jtag, but the console screen is empty.

Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation. But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur.

you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection

--- Quote Start --- Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation. But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur. --- Quote End --- I will try to do that, but I've also tried to run debug. The output says, that the processor is started, but when the debug window comes up, I see the processor "terminated". I don't know why is this happening. There are 4 critical warnings because of constraints, but those are common and not familiar with Nios. Something like clock uncertainty on JTAG TCK pin, actually can't remember now the exact warning... In addition, Nios now runs on 50MHz directly from the clock, so should be fine. --- Quote Start --- you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection --- Quote End --- Yes, I know, but this is used for mismatched systems, that are familiar. E.g. You use somewhere compiled .sof file, but generate Your own Nios code. This feature doesn't work, when the core is not running. ID and timestamp fields are marked "Not found". Thanks for the help.

Required Nios components | Altera Community

47 Replies

Altera_Forum
Honored Contributor
14 years ago
Are the byte enable signals correctly connected to your 16-bits SRAM? Looking at your text again, it seem that on each 16-bit word is in fact the second byte repeated twice (I don't know if it is very clear, expressed like that). It could be that when the CPU is trying to do a 8-bit write to memory using byte enables, the memory write the same byte twice instead.
It should be possible to test 8-bit writes using custom HDL or the system console tools.
Altera_Forum
Honored Contributor
14 years ago
Remember the nios will always do 32bit reads (with all 4 byte enables driven).
Altera_Forum
Honored Contributor
14 years ago
....im scared about it........

which board you are using??????
Altera_Forum
Honored Contributor
14 years ago
I can't actually imagine that the cpu would run well enough to execute the memory test code at all if the memory was generating errors like those shown.
Possibly that is some artifact of the JTAG uart interface itself, it ought to run happily at 50MHz without any pipeline bridges at all.
Altera_Forum
Honored Contributor
14 years ago
You need to constrain tck to run at at least 10MHz if you're using timequest (20MHz if you use the old timing analyser). The On-board USB-Blaster in the neek runs tck at upto 8MHz.

Also, there is probably little benefit to running the Avalon clock for the JTAG UART so slowly - I would run that at 20MHz or more (and check it meets timing)
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
I can't actually imagine that the cpu would run well enough to execute the memory test code at all if the memory was generating errors like those shown.
--- Quote End ---

The CPU only uses 32-bit reads to load the code, doesn't it? If there were a problem with byte enables as I suggested, it would mostly show up during I/O, but probably not before...
Altera_Forum
Honored Contributor
14 years ago
Here's another clue as to what might be happening...

When I program this:

int main()
{
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n");
printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n");

return 0;
}

I get this:

Hello from Nios II! 1234567890abcdefghijklmnopqrttvvxxzz

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz

eell rrom Nios II! 1234567890abcdefghijklmnopqrstuvwxyz

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz

Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz

Hello from Nios II! 1234567890abcdefghijklmnpprrttvvxxzz

eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz
Altera_Forum
Honored Contributor
14 years ago
I checked the signals on the JTAG port on my custom board. TCK is running around 6 MHz with the JTAG UART in Qsys running at 100 MHz. The Nios II CPU along with everything else in Qsys is also running at 100 MHz. No problems except this Nios II Console stuff.
Altera_Forum
Honored Contributor
14 years ago
Is the system running from on chip memory or external memory?
Altera_Forum
Honored Contributor
14 years ago
The Nios II software is running from external 516K x 16 SRAM.

I have an on-chip RAM block running as tightly coupled instruction memory in which I have configured the Nios II CPU to use for he reset and exception vectors.

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Required Nios components

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