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Altera_Forum
Honored Contributor
Honored ContributorRequired Nios components
Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory ...
Altera_ForumHonored Contributor
Honored ContributorI can't actually imagine that the cpu would run well enough to execute the memory test code at all if the memory was generating errors like those shown.
Possibly that is some artifact of the JTAG uart interface itself, it ought to run happily at 50MHz without any pipeline bridges at all.
