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Altera_Forum
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20 years ago

Problem using SDRAM

Hello,

I have problem using SDRAM on my custom board.

My program won't run when I map program memory(.text) to SDRAM.

I have no trouble reading/writing SDRAM from my program if .text is mapped to internal RAM.

I kind of have a feeling that this has got to do with

my setting SDRAM controller to:

"controller shares dq/dqm/addr I/O pins".

If I disabled this setting, not use external flash, and map .text to SDRAM.

then my program runs fine.

I had to choose "controller shares dq/dqm/addr I/O pins"

because my hardware shares data/address bus with external flash.

Any advice to solve this problem?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by fuji@Oct 20 2005, 06:40 AM

    i had to choose "controller shares dq/dqm/addr i/o pins"

    because my hardware shares data/address bus with external flash.

    --- Quote End ---

    Usually, folks give the SDRAM its own bus so other things won't slow it down.

    That said, I think there's a section in the SDRAM controller manual that says what you have to do to make the shared pins work, besides checking that box. SOunds to me like the SDRAM and Flash are conflicting with each other, being selected at the same time, or something. If it were happening to me, I'd have to hook up SignalTap or a logic analyzer to see what was happening. Sorry I'm not more help.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Thank you, Mike.

    We some how managed to solve the problem

    by shifting the phase of altpll.

    I don't know quite why...

    I will post again if I find anything new.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by fuji@Oct 21 2005, 06:42 AM

    we some how managed to solve the problem

    by shifting the phase of altpll.

    --- Quote End ---

    Yeah, you have to set that on a per-design basis. That phase shift compensates for delay in the non-clock lines to the SDRAM.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    hello!

    i have a very similar problem, my code is not running from my external RAM (SSRAM) and i am using a custom board. i cud not follow how u solved the problem, can u please explain what i should do to get it working.

    my opcode fetches are happening fine, but the stack pointer (fp) is pointing to an absurd address location.

    Thanks in advance,

    Raghu
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    What I think fuji did, is shift the phase of the clock feeding the external memory.

    Since there is a significant delay going off-chip to fetch data, and the memory is supposed to be synchronous with your processor, the clock-skew because of this delay is affecting the behavior.

    The clock therefore has to be phase shifted to compensate for this delay. For an example on how this is done, see altera documentation (http://www.altera.com/education/univ/materials/manual/labs/tut_de2_sdram_verilog.pdf)

    Since you are using a custom board, you will have to somehow figure out what the number (-3 ns in the above document) is for your board.

    --- Quote Start ---

    originally posted by raghuraman@Oct 24 2005, 04:06 AM

    hello!

    i have a very similar problem, my code is not running from my external ram (ssram) and i am using a custom board. i cud not follow how u solved the problem, can u please explain what i should do to get it working.

    my opcode fetches are happening fine, but the stack pointer (fp) is pointing to an absurd address location.

    thanks in advance,

    raghu

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10535)

    --- quote end ---

    --- Quote End ---