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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem booting program from EPCS flash and running from SRAM

Hardware and software tools:

NIOS II IDE 10.1 ("Legacy")

Quartus II 10.1

Device:Arria II GX - EP2AGX260FF35I5N

I am using software tools and hardware as described and a custom board.The problem as described in the title keeps popping up frequently in this forum so it might be a good idea to post the solution (step by step) in "Sticky" messages.Anyhow,i am facing the following problem - I have the FPGA and software tools and i also possess EPCS128 flash and 8 MB SRAM.I want to boot the Nios II program from EPCS and run in 8 MB SRAM.At this point i am able to run the program only in debug mode.In order to solve the issue I have tried the following solutions:

http://alteraforums.net/forum/showthread.php?t=20623 --->I have reached the point when i created the joint (concatinated) hw+sw bin file and i have no idea what to do next (I saw that this is impossible to burn that file to flash using the console programmer ,maybe some conversion is required?)

http://www.altera.com/support/kdb/solutions/rd12092009_471.html -->Trying to create .jic file and then burn that file using Quartus programmer.I have succeeded in doing this ,but the program still won't run after power-off and power-on,meaning it has not been programmed properly.Maybe the problem lies in the fact that the *.elf file used was from "Debug" directory and not "Release" (For some reason,the option of 'Release' has disappeared from IDE and i am not able to find that option anywhere).

Any help would be appresciated

Thank You very much,

Michael

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The "app_image.bin" file generated on the first link you give is the very exactly image of the data flash.

    you can try this, it could work : 

    nios2-elf-objcopy -I binary -O ihex app_image.bin app_image.hex

    and then program it with serial flash loader...

    [edit] I remove what I have write about the second link... it was wrong

    :oops:
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Here is the script I use to load up an EPCS with a FW/SW pair. The <EPCS BASE> should be the hex address of your EPCS controller component in SOPC Builder. (i.e. 0x04020000) Let me know if this helps. (as I can't send you a private message yet - too few posts:mad:) 

    #generate flash image for firmware <fw1>
"$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --input="<fw1>.sof" --output="<fw1>.flash"
# program <fw1> firmware into flash memory
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=<EPCS BASE> --cable='USB-Blaster ' --instance=0 "<fw1>.flash"
# generate flash image for <fw1> software <sw1>
"$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="<fw1>.flash" --input="<sw1>" --output="<sw1>.flash"
# program <sw2> into flash memory
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=<EPCS BASE> --cable='USB-Blaster ' --instance=0 "<sw1>.flash"
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    i have tried this method already(and the gui flash programmer method,which is almost identical),still without success.I guess the problem is either in sopc builder configuration or in the board itself

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In SOPC, what are your reset and exception vectors in the NIOS pointing to?

    My NIOS values are set to:

    Reset - EPCS Controller

    Exception - External RAM

    (I am assuming you have an EPCS controller block in your sopc project, it is required (normally) for the processor to boot from the EPCS)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    yes,i have checked about thousand times.

    Now i have set up an internal small RAM inside the fpga-the program boots from epcs and runs inside the on-chip RAM,so i guess the problem is in the access to external RAM
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I have the same problem. If I link my program to the SRAM, it doesn't boot, but if I link to the Onchip_memory, without change any other parameter or the script, it boots!

    I've checked what is written in the SRAM after boot, and it's not the right code, I don't no why! At the first direcction of the SRAm it should be:

    14008200 33000010 04F8BF10 16FDBF00

    However it's:

    140020A8 33002872 04F89739 16FD581E

    It's like it only writes the 16 first bits of every 32bits. Connections are right, because if I run it with Eclipse, it runs correctly! What's happening??
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yeap,the same exact problem here too.The weird thing is that i am able to run the program in the ram (or debug) (using the ide).With oscilloscope i am able to see data changing on address and data pins,but i don't see any data running on control pins of the ram (clk,ce,bwe,etc.) not in debug/run mode nor in regular mode

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Following the advice by altera support i have performed a memory test for my external SSRAM-this was the output :

    Testing RAM from 0x0 to 0x1FFFFF

    -Data bus test passed

    -Address bus test failed at address 0x80000