Problem about interval timer

With a clock of 20 MHz, that means only 20 cycles between the interrupt. I think this is not sufficient for the processor to make all the stuff it has to do (call of the interrupt service routine, make the job, and go back). You can verify this by simulation.

Can you use a higher frequency ?

Jérôme

Thank you for your advice.

I had enhanced the cpu frequency to 100MHz,but it didn't work.Now I think the problem may occur in the code.:confused:

If it works with a lower frequency, it seems that the problem is rather in timing than in code.

Which version of the Nios II do you used (e/s/f) ? Because they have not the same performance, so if you don't use the fastest one, maybe try to use a faster version.

Else I would say to check the behaviour in simulation, like that you can check if the Nios II can process the interrupt in the time allowed and if it is a problem of of timing or not.

Thanks a lot.

Now I set the cpu clock as 160MHz,and I set the timer period value in the Nios IDE.

It occurs a new problem,I set the timer as 0X0050,that means 80 clocks-- 2MHz sampling frequency.The result is 38KHz sine wave.

It confused me so much:confused:

From the Altera Documentation :

--- Quote Start ---

The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle.

--- Quote End ---

.

That mean a division by 81 instead of 80 that should produce interrupt rate at ~1975.3kHz and a sine wave frequency of 39.5 kHz (you have 50 points per sine period if I understand well).

So that does not correspond to your value but it is already a difference in relation to the theory. Maybe first try to toggle a pin at each interrupt to check the interrupt rate, and after that is verified, check your sine wave frequency.

Thank you a lot!

I do it as you said.But it still has some problems.

Now the cpu frequency is 160MHz,and I set the timer interval as:

IOWR_ALTERA_AVALON_TIMER_PERIODL(TIMER_BASE,0x0063);

IOWR_ALTERA_AVALON_TIMER_PERIODH(TIMER_BASE,0x0000);

and this means 100 divided-frequency.The result is not 40KHz but 13.36KHz.Besides,I set the

number as 0x031f(799),0x018f(399),0x00c7(199),then I watch the SignalTap II,found that when the number is 199 or 99,every timer interval is not equal.And when setting the number as 799,the result is 4KHz,399 as 8KHz,it's totally correct!

IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,0x0001);

IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,0x0002);

I can't upload the pic,I discribe it simply.In some periods 1 and 2 have less than 100 cpu clock periods.

I think the timedigram may have something wrong in it or the time settings in Quartus II is not met?

Hi,

Sorry for the silence, I was travelling.

What you described is quite strange, because normally the interrupt flag of the timer must be exactly at the same interval (it is just a counter inside). I don't know how SignalTap works I never used it, I always use ModelSim to check the behaviour, so i cannot help you a lot on this.

But since you have only problem with high interrupt rate, this should be a problem of timing. Which version of the nios do you use ?

Be sure the interrupt vectors are in on chip RAM, use the interrupt vector accelerator (the custom opcode choice in SOPC as it allows an indexed jump to the ISR, not a loop in C looking for the interrupt handler) and finally move your ISR into onchip RAM. You well could just be generating interrupts faster than the NIOS II can run them.

Bill

Thanks for you kindness!

I use the the fast nios cpu and the version of nios IDE is 8.0.Now I turn my way into designing the DA IP and add it into the SOPC systerm.As the same problem,I occur software problems,I couldn't get the correct result.Could you give some ideas about designing IP?

Thank you for help!

I will have a try.Besides I wanna ask another question:how to get the data or signal from avalon bus or how can I know the regiters of the SOPC systerm.

Thanks a lot! Sorry for troubling you!