printf() problem after IOWR and IORD

It requires a short time from when you send the printf and when the string is actually displayed in console pane because data needs to be trasmitted out of jtag uart. I believe the printf simply sends the data to the jtag driver transmit queue. So, if your program terminates before the transmission has completed, you will not see any data. Try adding a delay loop after the last printf, before exiting the program.

I added this loop after last printf():

 
for(i=0;i<9999;i++)
{
a=a+b;
}

Just add for (; ; ); you need the infinite loop!

I did your suggestion dsl,but nothing happened.

Are you sure that your avalon slave is actually terminating the slave cycles?

my slave custom logic is so simple because I'm just learning embeded design now.Is there any special signal that I must use in my module to tell to the cpu about termination? this module use one avalon_mm salve interface.

 
 `timescale 1 us / 10 ps
module new_component (avs_s0_address,avs_s0_read, avs_s0_readdata, avs_s0_write, avs_s0_writedata, avs_s0_readdatavalid,avs_s0_waitrequest, clk, reset);
  input   avs_s0_address;       
  input avs_s0_read;         
  output  avs_s0_readdata;      
  input  avs_s0_write;         
  input  avs_s0_writedata;     
  output avs_s0_readdatavalid; 
  output avs_s0_waitrequest;  
  input clk;                  
  input reset;    
 reg  A;
 reg B;
 reg avs_s0_waitrequest;
 reg  avs_s0_readdata;
 always @(posedge clk) 
 begin
  if(avs_s0_write && !avs_s0_waitrequest)
  begin
    A<=avs_s0_writedata;
  # 1 B<=A;
   end
   
 end
 always @(posedge clk)
 begin
   if(avs_s0_read && !avs_s0_waitrequest)
      avs_s0_readdata <= 32'b00111111111111111111111111111111;
  end
 
  assign avs_s0_readdatavalid = 1'b0;
   
  initial begin
  avs_s0_waitrequest = 1'b1;
 # 10 avs_s0_waitrequest = 1'b0;
 # 310 $display("A = %h hex", B);
  
  end
 endmodule
 

slacker,I know initial block is not synthesized at all,you are right,but I just simulate my design on modelsim.I mean. I run with modelmsim in the NIOS II IDE which sends the whole SOPC design as verilog files to this program,as you can see in the code the writing part (on reg A) uses wait_request signal after# 10 and after IOWR there is a prinf() which works,but just after IORD the cpu stalls! I attched the waves reported by modelsim.

Your code doesn't assert the readdatavalid signal. This is now hardwired to a low level.

According to the avalon specification document,readdatavalid is used for piplining the transfer,and it is not used in normal transfers,anyway when I assign logic '1' to the readdatavalid or remove it completely,the whole design stops during the simulation and these erros appear in the modelsim window:

#  245810 ns: WARNING: cpu_test_bench/M_wr_data_unfiltered is 'x'#  245820 ns: ERROR: cpu_test_bench/W_wr_data is 'x'#  Break in Module cpu_test_bench at ../cpu_test_bench.v line 522