printf() problem after IOWR and IORD

my slave custom logic is so simple because I'm just learning embeded design now.Is there any special signal that I must use in my module to tell to the cpu about termination? this module use one avalon_mm salve interface.

 
 `timescale 1 us / 10 ps
module new_component (avs_s0_address,avs_s0_read, avs_s0_readdata, avs_s0_write, avs_s0_writedata, avs_s0_readdatavalid,avs_s0_waitrequest, clk, reset);
  input   avs_s0_address;       
  input avs_s0_read;         
  output  avs_s0_readdata;      
  input  avs_s0_write;         
  input  avs_s0_writedata;     
  output avs_s0_readdatavalid; 
  output avs_s0_waitrequest;  
  input clk;                  
  input reset;    
 reg  A;
 reg B;
 reg avs_s0_waitrequest;
 reg  avs_s0_readdata;
 always @(posedge clk) 
 begin
  if(avs_s0_write && !avs_s0_waitrequest)
  begin
    A<=avs_s0_writedata;
  # 1 B<=A;
   end
   
 end
 always @(posedge clk)
 begin
   if(avs_s0_read && !avs_s0_waitrequest)
      avs_s0_readdata <= 32'b00111111111111111111111111111111;
  end
 
  assign avs_s0_readdatavalid = 1'b0;
   
  initial begin
  avs_s0_waitrequest = 1'b1;
 # 10 avs_s0_waitrequest = 1'b0;
 # 310 $display("A = %h hex", B);
  
  end
 endmodule