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Altera_Forum
Honored Contributor
15 years agoslacker,I know initial block is not synthesized at all,you are right,but I just simulate my design on modelsim.I mean. I run with modelmsim in the NIOS II IDE which sends the whole SOPC design as verilog files to this program,as you can see in the code the writing part (on reg A) uses wait_request signal after# 10 and after IOWR there is a prinf() which works,but just after IORD the cpu stalls! I attched the waves reported by modelsim.