Forum Discussion
Altera_Forum
Honored Contributor
15 years agoAccording to the avalon specification document,readdatavalid is used for piplining the transfer,and it is not used in normal transfers,anyway when I assign logic '1' to the readdatavalid or remove it completely,the whole design stops during the simulation and these erros appear in the modelsim window:
# 245810 ns: WARNING: cpu_test_bench/M_wr_data_unfiltered is 'x'# 245820 ns: ERROR: cpu_test_bench/W_wr_data is 'x'# Break in Module cpu_test_bench at ../cpu_test_bench.v line 522
how can I use this signal? In the document of avalon, there is an example which illustrates READ and WRITE transfers without using readdatavalid signal!