PLL of LVDS Clocking the Whole Design - SOPC Custom Component

Hi,

I am designing custom SOPC components for my board. One of those components is a controller for a fast ADC (2 x 1.6 GHz). Inside this component I have an ALTLVDS. So, I have the following clock design:

1. I have an ADC_CLK input @ 400 MHz at top level;

2. I route this ADC_CLK to the custom SOPC ADC controller via a conduit interface;

3. Inside the custom ADC controller I feed the LVDS with the ADC_CLK which (the LVDS, of course, has its own PLL). The PLL in the LVDS gives my CLK_LVDS @ 100 MHz;

4. I route this CLK_LVDS out via a conduit interface to the top level;

5. At the top level, I use CLK_LVDS to clock the whole design.

So the design works fine. I can even change the main frequency up and down a little bit. The problem is with fmax and the timing analysis. I have the feeling that the router and/or time quest don't do something right. I set one clock for timequest and this is the top level ADC_CLK @ 400 MHz. The problem is that it doesn't fit and gives me an fmax of approx. 105 MHz (should be 400 MHz as the 400MHz are only used for the LVDS).

So what am I doing wrong? How am I supposed to manually constrain all this? Or, shall I use some more elaborate SOPC approach?

Your opinions would be highly appreciated - I don't have much experience as a hardware designer.

Thanks,

-- Alex