PLL of LVDS Clocking the Whole Design - SOPC Custom Component

Yes, you're doing something very bad.

There's no way for you to know if the design will actually work reliably or not. It may work fine for a given FPGA at a given temperature and voltage and not work on the next one.

Note 1: there are performance differences between C7, I7 and A7 grades. Make sure you're not mixing them up.

Note 2: So, you have a 706 Mbit/s input rate. What _clocks_ are you actually using?

Note 3: After you sorted that out, remember to take a look at this document:

http://www.alteraforum.com/forum/attachment.php?attachmentid=201&d=1191905857