PLL of LVDS Clocking the Whole Design - SOPC Custom Component

Your design looks OK.

Top of my head:

You need to set a constraint for each clock at least. But you can just use the "derive_pll_clocks" command to set constraints for each of the PLL generated clocks.

A 400 MHz clock input is only supported if it's LVDS and it's the the maximum limit, at least for some devices.

Is your ADC_CLK a LVDS signal? Does your device support a 400 MHz clock input?

More than that, you'll need to check the paths that are failing to meet the constraints.