PLL of LVDS Clocking the Whole Design - SOPC Custom Component

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Yes, you're doing something very bad.

There's no way for you to know if the design will actually work reliably or not. It may work fine for a given FPGA at a given temperature and voltage and not work on the next one.

Note 1: there are performance differences between C7, I7 and A7 grades. Make sure you're not mixing them up.

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It is a C7 (EP2C70F672C7).

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Note 2: So, you have a 706 Mbit/s input rate. What _clocks_ are you actually using?

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The LVDS input clock (ADC_CLK) is 353 MHz (can be programmed up to 360 MHz via an external PLL). The C7 device seems to support up to 320 MHz. The PLL in the LVDS divides this by 4, so CLK_LVDS (this is the NIOS clock) is 88.25 MHz.

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Note 3: After you sorted that out, remember to take a look at this document:

(removed link because of bad carma)

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Thanks, I'm launching a Windows client so I can open it.