PLL of LVDS Clocking the Whole Design - SOPC Custom Component

Your advice is much appreciated. What you told me to do ("derive_pll_clocks"), saved me, probably, a whole day of reading the TimeQuest manual and the latter is not very interesting anyway.

So, I solved my fmax issues. I had to cheat a little bit though.

My FPGA is grade 7. The LVDS input sampling rate is 706 MHz (I told you 400 in my previous email because I set it so to fool the timing analysis).

When I set 706 Mhz for the LVDS (this results in 88.25 MHz for the rest of the design), I get an error that the maximum data rate for the LVDS is 640 Mhz. So, I go to the assignments and set a different FPGA device (grade 6, everything else is the same).

At this point everything fits smoothly. I even get some extra fmax.

So, I am overclocking the LVDS part with 10% and cheating about the FPGA speed grade. Am I doing something very bad and going to rot in hell?