PLL of LVDS Clocking the Whole Design - SOPC Custom Component

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What do you mean by GPIO LVDS?

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It seems like (from the document you referred to), that Altera Startix have an LVDS implemented in Silicone. The Cyclone series, on the other hand, use "soft" LVDS. Clearly, this makes a difference in the timing analysis.

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Are you using some kind of development board?

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Yeah. This is custom design software radio-like stuff. Dual 8-bit ADC (2 x 1.4 MHz), cheap FPGA (Cyclone II).

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Anyway.. if you already have the hardware up and running, try it. Otherwise, I'd replace the FPGA with a faster part.

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Thanks, I have already spoken to the guy who has designed the board and he told me that he is aware, and used the C7 only because C6 was not available at this time. Next revision of the board (if one is ever to be produced) will be with C6 and some other niceties.

Anyway, it seems to work, this is dev only, and I'm quite OK designing for C6 and running on C7 with 10% out of the envelope.