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Altera_Forum's avatar
Altera_Forum
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20 years ago

NIOS2 with 8Bit devices on tristate bridge

Outside the fpga is a multiplexed 8 bit device bus with shared

8-bit data

20-bit adr

nRD

nWR

and a couple of not shared nCS and a nINT to each device like LAN chip, Profibuschip, NVRAM, RTC ....

In sum there are 8 ( from nCS0 to nCS7 and nINT0 to nINT7) devices on that multiplexed bus.

Inside the FPGA is a NiosII V5.01

Within the SOPC builder i did the following setup :

i added an avalon tristate bridge and for each external device a custom sopc module that does only a translation of the external to the internal signals. I just added the external signals to the avalon tristate slave signals without any hdl coding and modified the class.ptf to have nRD and nWR with isshared=1

Now setting up signaltap to watch how different access cycles are handled give me the following conditions.

32Bit write access is performed as four 8 bit transfers. first is the lowest adr +0 ... accessing up to adr +3 This is OK as expected

16Bit write access is performed as two 8 bit transfers. This is also OK

and 8 single 8 bit write access is just one 8 bit transfer. So far so good.

A 32 Bit Read access is as expected performed by four 8 bit transfers.

BUT

A 16 bit read and a 8 bit read is always a four bit read transfer.

WHY ?

yes Nios 2 is a 32bit core. but assume external devices where you just want to access one 8 bit register and not all the registers folling the addresspace. imagie a read of a 8bit data register at adress 0 and a status register that is located at the next 8bit adress. a single read would read the 8bit adress 0 to 3. there are chips out there that will monitor the read of a register and clear bits within that adress range.

for such an external device it doesn't matter that nios forgets the not used bits from such a 32 bit read access when the software only needs 8 or 16 bit of them as coded (IORD_8DIRECT)

So how can i setup the sopc builder that an external 8bit device bus is accessed with only these operations that the software has selected. an 8 bit access regardless of read or write must perform only one 8bit access to the external device.

any help about that is welcome and urgently needed. this feature is a must have for us. we expected that this is possible. i have also send this to mysupoort as this is a very importand feature for us.

Regards.

Michael Schmitt

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Maybe it is the problem about native addressing v.s. dynimic addressing. Please take a loot at the latest avalon specification at the "bottom" page.

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    If I remember right I was able to eliminate this behavior on specific components (with a dedicated bus) by changing from 'dynamic' to 'native' alignment. I don't think this is going to be the answer for your multiplexed bus. The behavior is undesirable. So is this a bug in the Avalon implementation, a limitation of the design? I'd like to know too.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Thanks for your comments.

    I thought that i am aware of native vs dynamic address alignment. :-(

    Some of the external devices are memory and others not.

    We need to have

    external adr 0 = nios adr 0

    external adr 1 = nios adr 1

    external adr 2 = nios adr 2

    external adr 3 = nios adr 3

    all byte size.

    This is dynamic mode. but dynamic as mentioned on top of page 90 of the avalon specification says that a 32-bit master port read is two 16bit read on the slave port :-)))) that is what we would call a must not happen .... if software means 16bit then perform 16bit or twice an 8bit access

    native mode would produce some gaps as only the lowest 8 bit are valid

    nios adr 0 = ------AA = slave adr 0 = AA

    nios adr 4 = ------BB = slave adr 1 = BB

    so native mode is node the choice for us, a this would make it impossible for the software to use structs and other stuff that need the external memory being maped into the nios memory without any gaps or overlaping :-(

    so what i think right now is that the only solution could be :

    use nativ mode

    use the byteenable signals to determine what byte(s) are selected

    make datawidth 32bits to avalon

    and loop the external access until all selected bytes are accessed.

    what means that if software performs an 8 bit transfer the loop will do only 1 access and for 16bit 2 accesses.

    use waitrequest.

    this is a bit anoying.

    we have also some 512x8bit internal memory that is written by nios and read out by a verilog module. the other 512x8 memory is written by the verilog and read out by nios.

    so the verilog part needs the 8 bit access.

    nios must be able to access 8/16/32 bit whatever the software wants.

    it would be nice if a read performs like the write. if we write 8bit then there is only one 8bit write access. why can't nios/avalon do this with a read signal and set the "not" selected bits to 0 ?

    Has anybody a clue for this, i feel a bit lost about that.

    regards.

    Michael Schmitt